Physical Layout Design Engineer
Current• Independently assess and drive complex physical design assignments.• Working with circuit design engineers to interpret the schematics and implement in physical layout.• Build, modify and verify various levels of physical design hierarchy with verification tools using Cadence Virtuoso .• Perform pathfinding and floorplaning in projects and evaluate design options.• Actively involved in design rule check (DRC) clean ups, Layout Versus Schematic (LVS) debugs, RV/IR fixes. - Currently working on 7nm (SRAM). Previously on NAND Flash Memory.