Full time Hardware Design Engineer at IBM, with a recently completed masters degree in Computer Engineering from NC State University, focusing on ASIC Design and Verification, Computer Architecture and VLSI Design. Primarily working in memory subsystems and with high speed packetized interface protocols. Experience in many aspects of ASIC design flow including: Concept and High Level Design and Documentation RTL Entry in VHDL and Verilog Coverage Definition and Closure Timing Closure Pre and Post Silicon Debug Scripting using Bash, Perl, Python C/C++ OpenCAPI/OMI Interface Protocol DDR4/DDR5 Exposure to: PCIE/CXL UVM/SystemVerilog for Design Verification Cocotb Java Formal Verification Methods Synopsys Design Compiler Xilinx Design Tools/FPGA Design