Odd, Chi-Yuan Hung Email & Phone Number

中国 上海市

系统集成

Shanghai City, China

• Create and lead OmniVision Shanghai process team to setup first BSI line in China.• Helped to iron out 55nm FSI process issues and make it ready for production in 9 months.• Took ~2 months from tools move-in to get 1st BSI wafer operational.• Multiple process patents filed, system setup and B2B model and proposed.

Wuhan

• WuHan Fab deputy director (for F12 Operation) and module director of Beijing Fab B1, total ~1160 people.• Main products were Spansion 65nm Mirror-Bits NOR and Etox 90nm NOR Flash. • Capacity ramp up from ~ 3500 in Nov-2010 to 9000 wafer out per month in Sep-2011.• Successfully transfer Logic 65/55nm from Beijing to WuHan Fab with only 6 months taken.• Spansion 45nm Mirror-Bits NOR transfer PRS preparation.• Etox 65nm Nor Flesh transfer from Shanghai F8 to WuHan F12.• OCAP and SPC improvement ~20%.

Beijing City, China

• Module director of SMIC Beijing Fab, managing Litho, Etch, ThinFilm and Diffusion departments, total around 600 persons.• Sustain Fab harmony (between Modules, Module to Integration, and Modules with MFG)• Module KPI (line-yield, OCAP reduction, uptime, DN…etc) had steady improvements.• Introduced concepts of “Quick release” and successfully implemented on KrF09 and used same methodologies to help Fab B1 tools released to catch up with fast ramping up pace (as well as Starlight and CD-SEM skip rules generalization and risk control during machine capacity lacking).• Owner of TD module transferring to B1 for delivering Logic 55nm module supports.• Communicate with suppliers to smooth the service/support channels and B1 30/35k tool move-in situation.

Singapore

• (Nov. 2009~ Mar. 2010) To form and lead Immersion Taskforce, among Fab7 & TD & support teams, to identify the gaps & actions of the immersion area to help the 45/40nm ready for ramping up.• (Apr. 2008~ Oct.2009) Managing process integration for various customers on 65nm technology in Advanced Customized Technology III: Setup based line for Customized 65nm LPE process; IP verification; Ensure each prototype delivered to customer is a success; Yield and functionality demonstrated; Passed product reliability, and transfer to Fab for production.• Responsible for integrated post-Tapeout flow and RET studies for 45/40nm and below Advanced Customized Technology.• Manager of E-Test, Reliability & Product Yield technical support team in TD-ACT. And published 2 international technical papers.

Singapore

• CSM CTO office tape-out Integration technical consultant (especially on mask technology), mainly for 65nm customized technology.• Member of CHRT Patent Committee review board.• CTO of Jade Semiconductor (Shanghai) Ltd. (an OPC S/W startup company)• Published 2 international technical papers.

Shanghai City, China

• Published 7 (April) international technical papers.• Chairman of ECS-SEMI 2006 International Semiconductor Technology Conference (ISTC), Photolithography Session, Semicon China.• Developed 65nm OPC for Logic. • 45nm Logic RET/OPC study and strategy planning.• Work out 90nm and beyond SMIC DFM (Design for Manufacturing) flow Pattern related Scheme and Modification Loop methodology.• Provide SMIC manufacturing Fabs with cost effective OPC H/W and S/W, and working on Fab-to-Fab patterning matching and new Fabs OPC treatment strategies.

Shanghai City, China

• Published 15 international technical papers.• Held several oral presentations & OPC training classes for inside and outside SMIC.• Developed 90/65nm Logic OPC.• Submitted several Patents.• One of SMIC Patent Committee members to review SMIC applicant's patent application for Photo, Mask, RET and OPC related fields.• Received “Program management” training and won the “top 3 best HW award”.

Shanghai City, China

• Mentor and lead all OPC department members.• Setup all OPC hardware & software infrastructures.• Won “LTD Outstanding Engineer” award.• Published one technical paper and held Photo-OPC training classes for all SMIC employees.• Submitted and got accepted more than 10 Patents.

Shanghai City, China

• Developed 0.18um, 0.15um Logic product FEOL photo process.• Developed 0.13um Logic product FEOL rev.1 photo process.• Setup all SMIC 0.18, 0.15, 0.13um critical layers OPC by myself.

• Developed 0.25um, 0.18um Logic product Photo Condition.• Setup NA/Sigma Optimization Flow via the concept of Pupil Analysis.• Developed rev.1 Photo condition for 0.25um SOC product.• Published over 10 internal technical reports and papers.• Submitted and got accepted over 10 Taiwan Patents.

Master Of Science (M.S.), Physics

Bachelor Of Science (B.S.), Physics