Ofer Shacham Email & Phone Number

Hod Hasharon, IL

Tel Aviv, IL

Giving back by teaching the VLSI class, at the same place where I started

Ramat Gan, Israel, IL

Menlo Park, CA, US

Menlo Park, CA, US

Menlo Park, CA, US

In ARVR, industrial design and thermals are *the biggest* design constraint. That means hardware defines the limits of what software can accomplish. Our job is to create compute platforms that give the world seamlessly blended virtual and real experiences. To make science fiction real!Our team creates high compute, low power SoCs. We take a broad and.

Menlo Park, CA, US

Menlo Park, CA, US

Mountain View, CA, US

Head of Silicon Design and Implementation in the Silicon Group of Consumer Hardware. Key team expertise include: Imaging, Computer vision, Machine Learning, Security, Video Compression.Key sub-teams: RTL Design, HLS Design, Design Verification, Silicon Infrastructure, Prototyping & Emulation, Bring-up, SoC Integration, Physical Design

Mountain View, CA, US

Enable Google’s continuous innovation in image processing and machine learning in mobile. We created a new computer architecture, capable of delivering multiple Tera-ops/sec at a power budget of a cell phone.

Mountain View, CA, US

- Integration of Chip Genesis Technology at Google- Innovative digital and mixed signal design for cool new products

Stanford, CA, US

Managing the DARPA funded "Specialized Extremely Efficient Computing" grant for Professor Mark Horowitz at Stanford. In this proposal we are creating a software and hardware design approach that enables creation of application-optimized hardware for much lower design costs. We will use this system approach to demonstrate an image processing system two.

Stanford, CA, US

DARPA funded SEEC: Specialized Extremely Efficient Computing Grant. In this proposal we are creating a software and hardware design approach that enables creation of application-optimized hardware for much lower design costs. We will use this system approach to demonstrate an image processing system two orders of magnitude more efficient than using today’s.

Stanford, CA, US

Research Assistant - Department of Electrical Engineering, Stanford University. Currently working on the Chip Generator project (http://chipgen.stanford.edu/). I'm trying to figure out how to architect, design and verify chip generators and generated design instances.

Stanford, CA, US

Research Assistant - Department of Electrical Engineering, Stanford University. Currently working at the Smart Memories project (http://www-vlsi.stanford.edu/smart-memories). My role is to lead, define and design the verification efforts of the Smart Memories system.

Chip Genesis Inc. is a Stanford University spin-out enabling digital chips with improved power efficiency and reduced design costs. Acquired in August 2013.Making ASICs, SoCs or CMPs today can cost in excess of $50 Million, and those costs are expected to rise to $140 Million in 3-5 years. In order to contain and reduce these costs, Chip Genesis seeks to.

CA$HSTREAM is developing a high performance computing platform to accelerate numerical routines for financial applications by 50-100X compared to currently available products. The CA$HSTREAM solution utilizes energy efficient multi-core GPU hardware and does NOT require rewriting legacy code originally written for traditional x86 CPU architectures. Initial.

Santa Clara, CA, US

Summer internship (while doing my PhD)The job focus was dual: Chip bring-up for a top of the line NVIDIA GPU and timing closure for a newer version of the GPU chip. Both chips were manufactured in 65nm technology.

Armonk, New York, NY, US

IBM - Research & Development Lab., Chip Design Group, Israel. As a member of a chip design group, I worked on various ASIC design projects. Mainly I dealt with verification issues.

Diving Instructor at "Dugit-Octopus Diving Club Ltd", Herzliya, Israel

Phd, Electrical Engineering

Masters, Electrical Engineering

B.S., Electrical Engineering & Computer Science

Bachelor'S Degree, Electrical Engineering And Computer Science