Oh Tepmongkol-Wheaton Email and Phone Number
Oh Tepmongkol-Wheaton work email
- Valid
Oh Tepmongkol-Wheaton personal email
- Valid
I am a Social Commerce Fashion Tech Strategist and a Forbes Next 1000 Honoree. I help IRL fashion brands bring the intimate experience of their products across all metaverses. I am a seasoned veteran with 30 years of experience as a computer graphics architect and principal engineer at top fortune 500 companies. I co-founded OHZONE, a 3D fashion tech startup that has been awarded Top Fashion Tech 2021 by Retail Tech Insights, covered in the Vogue Startup Spotlight, and one of the Top 200 for Tommy Hilfiger Fashion Frontier Sustainability Challenge 2021. I am also an Executive Director for the charity NFT digital fashion runway show to benefit One Warm Coat in Dec 2021 as mentioned in the CoinTelegraph Wear-To-Earn article. Our patented 3DREALTM technology teleports fashion collections to the next generation of consumers in any digital realm of their choosing. We bridge the gap between real and digital fashion experiences for e-commerce, AR/VR, and meta-commerce.OHZONE was founded initially from my desire to stay connected with my daughter, who went to college on the opposite coast. We were having difficulty shopping online for clothing together. The clothing we looked at together online lacked the detail and subtlety she desired in 2D imagery. I decided to apply my skills in 3D algorithms and video graphics to create a better shopping experience. When we first built our prototype and showed it to my GenZ daughter, she and her friends played with it for two hours straight during a Thanksgiving dinner. That experience confirmed that we created something magical.We spent 24 women years developing the patented 3D photorealistic called 3DREALTM technology to create true-to-life digital assets from real garments. Today, OHZONE is a fully operational company with a team of engineers, marketing and sales — all inspired by a dream to bring 3D virtual fashion to life.
-
Ceo And Co-FounderThe Ohzone, Inc.Santa Clara, Ca, Us
-
Ceo/Co-FounderThe Ohzone, Inc. Sep 2014 - PresentSunnyvale, Ca, UsThis is my moonshot startup. I am grateful for all my friends and advisors who help and support us over the years on this road to realizing this dream.OHZONE democratizes meta-commerce by enabling IRL fashion brands to create an intimate online experience of their products, with the quality and aesthetic only possible in the real world, across all metaverses. Our patented 3DREALTM technology teleports fashion collections to the next generation of consumers to hold, inhibit, and wear in any digital realm of their choosing. We bridge the gap between real and digital fashion experiences for e-commerce, AR/VR, and meta-commerce.
-
Beta UserThe Fourth Floor Jan 2021 - PresentNew York, New York, UsThe Fourth Floor is a new kind of membership community where womxn leaders and startup founders create and access board seats, investments, and funding opportunities. We democratize access to under-the-radar startup board seats and investment opportunities by leveraging community and a digital platform, as a way to create wealth and drive systemic change. -
Design Verification ConsultantCadence Design Systems, Denali Ddr Ip Group Dec 2013 - Aug 2014San Jose, California, UsPerformed verification of High Speed DDR PHY using UVM. The includes enhancements for testbench and sequences for fly-by leveling per chip select and DFS for DDR3, DDR4, and DIMMs. Run and debug regression for Customer IP delivery. -
Consultant, Asic Design And VerificationIntel Corporation Apr 2012 - Oct 2013Santa Clara, California, UsModphy HARD IP: Modified TX swing controller in the Universal Phy IP core to accommodate PCIE Gen3. This includes designing of rate dependent margin, deemphasis, back-channel access, and Duty Cycle Correction controller, updating the ULT, and creating additional tests and testplan. Optimized the design for low power by minimize retention cells and enable clock gating. Designed analog interface for process monitor, ADC, resistence compensation. Added assertions for inter block protocol compliance, and retention checks for interface and calibration results. Supported chip and gate level debug.Video Analytics IC: Support Video Captures Interface unit for the Video Analytics chip (TSMC 65gp), intergrated Video Capture Interface verilog models into system verilog testbench and help bring-up video captures interface for emulation. Created Primetime chip level constraints for pre and post CTS. -
Consultant, Fpga Architecture And DesignPdf Solutions Jun 2011 - Apr 2012Santa Clara, California, UsStablized and debugged the Virtex 6 FPGA with PCIE Gen2 and 32 channels interface to Analog Control circuitry for high speed wafer characterization. Assist in transition this design from external design house to internal. Review the arithmetic pipelines and built specialized testbench. Extensive modification to enhance the data transfer over PCIE to PC for speed and reliability. Built hardware to synchronize 256 channels across multiple boards. -
Consultant, Fpga Design And VerificationNextnav Llc Jul 2011 - Feb 2012Reston, Virginia, UsSupport design enhancements and testing for the Transmit FPGA using Spartan 3A and Spartan 6 with microblaze. Build the verification testbench for vectors matching between matlab filter models and RTL.Add one wire interface for Temperature sensor. Support bench testing with python scripts. -
Principal EngineerRgb Networks Nov 2009 - Apr 2011Sunnyvale, Ca, UsArchitect the system data flow for simultaneous 160 6-MHz channels broadcasing that is in compliance with MCMAP cable specification. Architect the FPGA (Virtex6) which performs J.83 framing structure, channel coding (excluding modulation), multi-mode interleaver, encryption engines for DES and AES, for both 64-QAM and 256-QAM. Specified interfaces to PCIE and 1066 MHz DDR3. Effective at resolving 7 legacy system bugs that required working with cross function personnel and debugging hardware and software with virtually no documentation. Proposed an innovative video quality enhancement for VMG products utilizing existing on-board hardware. -
Store OwnerPlay N Trade Video Games 2007 - 2009San Clemente, Ca, Us -
Consultant, Fpga ArchitectureTessera May 2007 - Sep 2007San Jose, California, UsArchitect the auto-focus imaging pipeline for cellular phone application. Implemented the control path with low-power features. Wrote test plan, specified tests and testbench. Created module level tests and testbench. Performed FPGA gate level simulation. Reviewed Leda logs, synthesis results, and coverage -
Consultant, Asic Design And VerificationExtreme Networks Jun 2006 - May 2007Morrisville, Nc, UsDesigned and verified a parameterized multi-lane serdes interface to IBM HSS core operating at 312.5 Mhz in Cu08 technology. The transmitter of the multi-lane interface frames the packet data, computes the crc, and spreads the data across upto 5 serdes lane according to specified parameter. The receiver aligns the data across the lane, detects the framed packet and crc, and drops the bad crc packets. The 8b10b codec unit interface with IBM HSS core, detects comma characters and disparity errors according to the IEEE 802.3 standard. -
Consultant, Fpga Design And VerificationHarmonic Nov 2005 - May 2006San Jose, California, UsBring-up verification environment for the HD/SD video FPGA. This task includes updated existing tests, enhanced the existing verification models for speed and additional functionalities, and verified and/or modified the expected results appropriately. Created tcl regression script for use with Modelsim in a PC environment. Created PCI local testbench for error testing. Wrote fast simulation models to emulate Altera DDR2 core and PLL cores. Created programmable video generator/capture model and audio inserter/extractor for HD and SD. Assisted in testing and integrating Altera DDR2 400Mhz core. Integrated Ateme’s CABAC core into existing FPGA design. This task included adding clients to Altera’s PCI core and SDRAM controller (at 75MHz) as well as expanding DMA engine capabilities. -
Senior Member Of Technical StaffZoran 2003 - 2005Sunnyvale, California, UsWorked closely with CTO to reduce white paper concept to working video system architecture. Specified micro architecture the scalable Display Processor Unit for all-format NTSC/PAL/ATSC analog/digital video outputs. Defined video pipeline architecture/implementation for Digital VCXO tracking system. Also defined micro architecture for the auxiliary display channel. Led a small team to design and verify the Display Processor Unit. Defined and helped created rigorous verification environment consists of randomize local testbench and unit level testbench. Designed and verified the programmable display composite and pipe control sub-unit, analog resampling sub-unit, sync buffer sub-unit, graphics scaler sub-unit. Also defined, designed, and verified horizontal anamorphic scaler. Helped designed and/or verified video scaler with programmable filter taps sub-unit and auxiliary scaler sub-unit. -
Consultant, Fpga EmulationBroadlogic Jan 2003 - May 2003UsFPGA emulation of downstream Docsis Physical Layer design with Xilinx VirtexII. -
Senior Member Of Technical StaffCoppercom Jan 2000 - Jan 2001UsDefined, designed, implemented, and verified T1/E1 Signaling FPGA. This includes GR-303 and TR-08 signaling block, HDLC interface, microcode sequencer for signaling post-processing, DMA block, host interface, Infineon QUAD FALC framer interface (H100), Echo canceller interfaces, and TI DSP intf. -
Senior Member Of Technical StaffTerayon 1999 - 2000UsArchitect IEEE802.14/Docsis 1.2 Upstream Physical Cable Modem ASIC pipeline. Led the team in design and verification of the ASIC. Implemented TDMA byte, sub-symbol, and bit interleavers, preamble, SCDMA framer, SCDMA spreader with code hopping, pipeline control logic, profile controller, and shared SRAM controller. Wrote custom PLI routines for verification environment. Chip level verification of second generation Upstream Physical Cable Modem ASIC Chiplet. Correlated lab bench testing with simulation tests. Created and ran fault/error condition tests. -
Senior Member Of Technical StaffTeralogic 1998 - 1999Designed/modified memory and DMA interface to Phoenix PCI core. Created and performed Chiplet testing, which included writing microcode for MIPS 64K core, proprietary Audio DSP block, and general purpose I/O sequencer. Wrote focused block tests for DDR Memory Interface. Assisted in architecture and implementation of the host interface portion of the HDTV ASIC. Designed, implemented, and tested NTSC Video Scaler/Capture Unit Also ported existing Bit Blitting unit and Audio Processing unit. Performed chip level static timing analysis using Primetime and Design Compiler.
-
Senior Member Of Technical StaffPixelerate, Inc. Jul 1997 - Apr 1998Architect color image pipeline for document imaging system. This includes color correction, halftoning, scaling, and image enhancement and color conversion algorithm.
-
Senior Member Of Technical StaffParc Nov 1996 - Jul 1997Palo Alto, California, UsParticipated in chip level verification for an image path ASIC for color copier. Prototyped high addressibility with new laser engines using Xilinx FGPA. -
Research & Development EngineerHewlett-Packard, Personal Printer Division Sep 1989 - Oct 1996Houston, Texas, UsDigital ASIC Design: Responsible for ASIC implementation of proprietary imaging and compression technologies in a super integrated (68EC030 core) ASIC. Board Level Design and Simulation: Developed, simulated, and regulation tested the imaging hardware platform for the LaserJet 5L. Performed hardware board level simulation and system timing verification for LaserJet 4P and LaserJet.Hardware Test Design: Developed code for testing hardware functionality of several printer controllers. Designed and developed Board-level Environment Stress Test (BEST) hardware for LaserJet 4P, LaserJet 4MP, LaserJet 3P, and LaserJet 3.Product Transition: Helped transition LaserJet 4P and LaserJet 4MP hardware platform from development phase to manufacturing phase. This includes finding root cause of component failures; qualifying new component vendors, improving test coverage, and training debug technicians.
Oh Tepmongkol-Wheaton Skills
Oh Tepmongkol-Wheaton Education Details
-
Y Combinator Startup School -
Stanford UniversityElectrical Engineering
-
Texas A&M UniversityElectrical Engineering
Frequently Asked Questions about Oh Tepmongkol-Wheaton
What company does Oh Tepmongkol-Wheaton work for?
Oh Tepmongkol-Wheaton works for The Ohzone, Inc.
What is Oh Tepmongkol-Wheaton's role at the current company?
Oh Tepmongkol-Wheaton's current role is CEO and Co-founder.
What is Oh Tepmongkol-Wheaton's email address?
Oh Tepmongkol-Wheaton's email address is oh****@****inc.com
What schools did Oh Tepmongkol-Wheaton attend?
Oh Tepmongkol-Wheaton attended Y Combinator Startup School, Stanford University, Texas A&m University.
What skills is Oh Tepmongkol-Wheaton known for?
Oh Tepmongkol-Wheaton has skills like Asic, Verilog, Fpga, Soc, Firmware, Hardware Architecture, Perl, Static Timing Analysis, Systemverilog, C, Semiconductors, Ic.
Who are Oh Tepmongkol-Wheaton's colleagues?
Oh Tepmongkol-Wheaton's colleagues are Disha Das.
Free Chrome Extension
Find emails, phones & company data instantly
Aero Online
Your AI prospecting assistant
Select data to include:
0 records × $0.02 per record
Download 750 million emails and 100 million phone numbers
Access emails and phone numbers of over 750 million business users. Instantly download verified profiles using 20+ filters, including location, job title, company, function, and industry.
Start your free trial