Nodeflux Indonesia is a leading artificial intelligence company specializing in computer vision. We offer innovative solutions for analyzing video data using deep learning techniques. With a focus on intelligent video analytics and custom solutions, Nodeflux has achieved significant success in various industries, including government, law enforcement, intelligence, and defense. Our commitment to research and development has positioned us as a prominent player in the field of AI.My role:- Product and technology strategy- Principal architects (Computer Vision, Distributed Computing, AI Platform, and Video Compression Technology)- Organizational strategy and people managing

Managing and leading roles:• Ensuring technology team success in delivering product in terms of quality, schedule, and technical innovations• Contributing in engineering hiring pipeline and process• Influential in defining team structures, separations, and job functions to ensure team resilience, agility, and focus• Growing team, front line engineers, and engineering managers through management and mentorship(1:1, Retrospective, Engineering all-hands)• Influential in driving discussion of engineering values and its resulting working culture in the processesTechnical contributions:• Influential in driving architectural designs and its optimizations in the area of backend infrastructures (Cloud and Kubernetes-based deployments and its surrounding infrastructures ) and computation platform implementations• Hands-on development on key common modules, libraries, and base platforms for Nodeflux’s Computer Vision Real-time Analytic System(Visionaire). Developed using modern C++ and various supporting stacks like OpenCV, Boost, Pytorch, and Golang

Managing and leading roles:• Lead, manage and mentor OY! engineer teams and related personnel in translating company's technical direction into daily activities• Working closely with VP of Product and PMs in managing and defining resources allocation/schedule to meet the KPIs of deliverable products• Owning engineering process, priorities, based on both short-term and long-term goals• Oversees overall OY! system architecture to accommodate reliability, scalability and security expectations• Grow the technical teams by owning technical hiring process• Helping develop and manage engineering personnel capability of carrying out initiatives and helping them to growTechnical roles:• Own/directly involved on core communication(chat+voice) subsystem designs and its implementations in Erlang• Identify competitive services and opportunities for innovation

• Lead and hands on-involved on development of VoIP transcoding server, SIP Session Border Controller(SBC), and VoIP/SIP load balancer(all using C/C++). • Develop and maintain operation ofIP video broadcasting/streaming server(HLS/RTSP). • Develop real-time messaging server using ejabberd/erlang OTP. • Maintains and provision cloud based server infrastructure in scalable and automated fashions(server provisioning using Ansible, load balancing, high availability with HAProxy and custom load balancer and other automation scripts).

Oversee, maintain and develop mobile telecommunication core network system software for MVNO operation. One of their product is Vectone and Vectone Mobile.My role:• Cut company cost by implementing software-based media processing(transcoding and essential RTP codec supported) to replace media card based processing.• Develop and maintain subscriber home database(HLR/HSS), Switching Gateway(GMSC/IWMSC), packet switching gateway(GGSN/PGW)• Develop and maintain lower level C++ drivers: ISUP, SIP, Diameter, MAP, HTTP act as Server/Client, DNS client, Voice Switching Card(Prosody), and Virtual Machine module(above which the higher level software/script can run and use all the low level APIs)• Core system migration from 2G/3G based core network to 4G/LTE EPS core network. This involve development of required core network modules• Develop SIP extension required to be used for Voice over IMS/LTE• Develop and migrate implemented network authentication from old COMP128 to 3G and 4G Milenage authentication.Skill set: MVNO System, Native C++ telco software development, RFC3261/SIP based VoIP,Sofia, GSM/UMTS Core Network, LTE EPS Core Network, IMS, ISUP,Diameter/MAP, HSS, HLR, 3GPP Standards

Develop from scratch an implementation of JavaCard Virtual Machine, Runtime Environment, and API based on JavaCard 2.2.2 specification. The implementation, written in C, is targeted to small 8051 or ARM microprocessor with all bytecode linking process done in target system(applet installation), but not when execution time. The Virtual Machine and Runtime Environment support:• Complete JavaCard bytecode execution• Virtual function and interface function invocation• Classes and interfaces derivation• JavaCard execution context and firewall protection• Persistent and transient object creation• Atomic data updating• Inter-package class and bytecode linking• Inter-package execution context switch• Extensible Javacard API(classes/methods/interfaces) to allow both native API development and advanced API(global platform, sim toolkit, etc)Skill set: C, JavaCard, Virtual Machine and Runtime Environment for smart card devices.

• Develop advanced features for C++ implementation of Session Initiated Protocol(SIP)/RFC 3261. All upgraded features are related to improve compliance to 4G/IMS-supported devices/network consisting: a. Profile A(SIP/RFC3261, media negotiation, Indentity/privacy, session updating) b. Profile B(overlap call support) c. Profile C(ISUP encapsulation/decapsulation to/from SIP packets)• Develop VoIP desktop client application using C and C# combined. This client application facilitate user to make call to another user on internet, or mobile number.• Support for GSM system maintenance/troubleshoot (Mobile originated/mobile terminating SMS. HLR location update, etc)• Create low level SMS handling driver in C++ and build its wrap interface so it can be called from higher layer, .NET application.Skill set: C++, Design patterns, SIP, IMS/3GPP standards, GSM system, .NET(C#)

• Eliciting hardware and software requirements for chip design products• Planning of hardware and software architecture consists of hardware and software interfacing, processor, bus and peripherals architecture in a system-on-chip design, host PC driver development and application software• Development planning, time and target scheduling, resource allocation• Hardware and software verification strategy for quality assurance acceptanceSkill set: Product development management, quality assurance, system analysis

• Architecture design of sytem-on-chip consisting two 32-bit processors, three bus, and peripherals including WiMAX e PHY. The design goal is good data transfer efficiency and subsystem separation, while maintaining perfect memory coherency between processors and DMA.• Design digital RF interface to be used with AD9354 RF transceiver product• Design double-clock edge digital ADC/DAC interface• Design asynchronous-clock interface for smart card ISO signal to microcontroller• System-on-chip implementation on Altera FPGA, pin planning, floorplanning, timing constraining and technology mapping• RTL Design and Implementation of WiMAX 802.16e subcarrier allocator and forward error corection components• Develop asynchronous-clock interface of USB Device controller to be used with Amba AHB busSkill set: Embedded Software(C), WiMax 802.16e, Custom system-on-chip(SoC) development, micro-architecture design(register transfer level), FPGA, digital to RF interfacing, USB hardware and software development

• Design and implementation of harsh breaking detection algorithm in C for an embedded system project. The algorithm utilize constant data stream that come from accelerometer chip• Develop an embedded software driver for 1-wire bus and its devices. The driver supports device enumeration, data integrity check, and register access• Develop an embedded software driver for accelerometer, serial flash, and serial RAM. The driver will be integrated to RTOS and run on both Texas Instruments's Stellaris ARM series and Fujitsu ARM• Develop Windows Network Driver, based on NDIS with Windows Kernel-Mode Driver Framework(KMDF)• Develop Platform for Integrating Hardware(HDL) and Software co-simulation to speed up System-on-Chip development cycleSkill set: Real-time OS(RTOS), High performance and low latency programming, Windows device driver development(using KMDF), ARM programming

The purpose of this project was to track poultry distribution for further analysis to prevent the spread of avian influenza virus. The most of development focused on mobile application technology like Brew and Java. This project also utilized of GIS for accurate mapping and tracking the spread of distribution.Skill set: mobile application programming using Qualcomm's Brew platform(C), web programming using PHP

Develop Digital Filter Implementation Using Texas Instruments DSP Board