🌟 Excited to Share My Summer Training Experience with National Telecommunication Institute (NTI)! 🌟I’m thrilled to announce that I’ve completed an enriching summer training program with NTI, where I delved into the fascinating world of digital design! 🚀Here’s a snapshot of what I learned:📍 State-of-the-Art Programmable Logic and FPGA Technology📍 FPGA vs. ASIC Designs📍 Introduction to VHDL Language📍 Concurrent Statements, Components, and Data Flow📍 Scalar and Composite Data Types and Operations📍 Sequential Design and Simulation Methodologies📍 Sequential Statements: Conditioning, Looping, and Waiting📍 Basic Test Bench Creation📍 Finite State Machine Design📍 Advanced Test Bench Development📍 Building Memory: Distributed and Blocked Memory📍 Attributes, Functions, and Procedures📍 Packages and Libraries📍 Design for Synthesis📍 🚀work on xilinx spartan-3e fpga board and go through the fpga flow🌟💻This experience has significantly expanded my skills and knowledge in digital design and hardware description languages. I’m eager to apply what I’ve learned and explore new opportunities in this dynamic field!

I’m happy to share that I have successfully finished an intensive 3-months Digital IC Design course supervised by Eng. Ali M. Eltemsah with an Excellent Grade📌we go through many important topics as:- ➢ Learn how to write a synthesizable and efficient RTL using verilog ➢ how to write an advanced Test-bench and do functional verification ➢ TCL Scripting Language ➢ How to do Static Timing Analysis for all different paths in the design and explain the concept of hold time , setup time recovery time and removal time and uncertainties as clock jitter and skew ➢ Understand Low Power Design Techniques as clock gating cells and other techniques ➢ Understand Clock Domain Crossing and metastability concepts and how to solve it using synchronizers and fifos ➢ How to do synthesis for the rtl design using design compiler tool and learn how to read reports ➢ Design For Test (DFT) and understand the concept of scan chain and scan flip flops ➢ Formal Verification Post-Synthesis & Post-DFT & Post-PnR ➢ Floorplanning, Pin Placement, Clock Tree Synthesis, Placement, Routing, Chip Finishing, Sign Off ➢ Gate Level Simulation➢ how to deal with the asic tools📌Final Project: “ Implement a low power multi clock system from rtl to gds”.

I'm thrilled to announce that I've completed the Digital IC Design Workshop With semicolon.▫We've discussed alot of interesting topics as:- Digital Design flow.- Combinational Logic circuits & how to design them in Verilog.- Sequential circuits & how to design them in Verilog.- Verification using Verilog & testbench generation.- Finite State Machine (FSM) & Memories.- Verilog synthesis constructs.▫Project:-At the end of this workshop i also implemented an arithmetic Logic Shift Unit (ALSU) using Verilog and test bench to verify its functionality.