Omar Haddad Email and Phone Number

• Provide consultation services to NASA-GSFC in the areas ofdesign verification, SpaceWire designs, systems design, FPGAdesign, and Total Verification System Ground SupportEquipment usage.• Oversee the production and sales of Total Verification Systemunits to federal agencies.• Conduct business operations including accounting, webhosting,invoicing, taxes, contracts, and product development.

• Architected, designed, and developed high-speed customGround Support Equipment components and several IntellectualProperties VHDL and C++ cores for the purpose of testing andverifying flight instrument hardware on the ICESat2 mission.• Designed a flexible and programmable, general purpose, rackmountable, Ground Support Equipment, named TotalVerification System, TVS, that improves the digital designprocess and builds on the C++ based verification environmentdescribed below.• Used TVS to verify the operation a single board processordesign for the Magnetospheric Multiscale mission, MMS, andthe S-Band communication card for Global PrecipitationMeasurement, GPM, mission.• Architected, designed, and developed the electronics hardwarefor a technology demonstration project developing a bridgebetween a SpaceWire communication link to SpaceFibercommunication link capable of 1-Gbps bandwidth.• Designed and implemented a unique verification environmentfor LRO CDH that encompasses both simulation and lab testingand is easily portable to future missions.• Completely architected, implemented, and verified anInstrument Interface Actel RTAX2000 FPGA for the LRO CDHsubsystem.• Wrote and executed a thorough C/VHDL verification plan toverify an IEEE 1355-2 SpaceWire bus router targeted to anASIC.• Designed an advanced verification environment for the digitaldesign department of NASA’s use. Included was a C/VHDLgasket that allows communication between tests written in Cand VHDL designs.• Implemented Rice’s lossless data compression design into aRadiation-Tolerant Actel FPGA using VHDL RTL. Target clockfrequency 40MHz.• Provided consultation for a UTMC ASIC design for Swiftmission.• Prepared various documents for the James Webb SpaceTelescope mission including design specifications, test plans,requirements, and interface control documents.• Performed feasibility studies for compression algorithms, GPSarchitectures, and data processing units.

• Designed ASIC cores to implement DSL technology forcomputer modems and central office line cards.• Worked closely with customers such as Intel, Infineon/Siemens,and AMD/Legerity through our entire ASIC flow (COREspecification, RTL design, verification, synthesis, floor-planning,layout and timing). Aware’s cores were fabricated using 0.25and 0.18μ techonology.• Wrote detailed specification documents for our ASIC cores.• Designed cores in using VHDL and Verilog RTL (over 50000lines of RTL code) with emphasis on IP reuse. This was donewith strict coding guidelines and database organization.Optimized design for speed and area using methods likepipelining and resource sharing.• Wrote verification plan documents for testing of our ASIC cores.• Verified designs with custom built SW/HW co-simulationenvironment using C and Modelsim/Leapfrog/NC-VHDL. Ourthreaded cosim environment was built to allow our tests to bewritten in C and communicate through a UNIX socket to theHDL simulator. This allowed us to test our software andhardware simultaneously by writing tests in C (over 100000lines of C code).• Designed bus functional models of hardware that interfaces withour ASIC cores (over 20000 lines of behavioral VHDL code).These models were designed to communicate using VHDLforeign language interface or Verilog programmable languageinterface.• Wrote Synopsys synthesis scripts for our ASIC cores specifyingfalse paths, mutlicycle paths, input load capacitance, etc.Performed static timing analysis to verify that timing was met.• Performed formal verification between VHDL and Verilog as wellas RTL to synthesized gates.• Mapped our ASIC cores to Xilinx FPGA’s for design emulationand concept validation.• Obtained expert knowledge of Utopia bus protocol and ATM cellformat, structure, and usage.• Worked with VHDL to Verilog translation tools, Makefiles, PERLscripts, and revision control tools.