I work with Intel & Synopsys Design tools to take design partitions(IPs) from an abstract RTL model to a fully synthesized and functionally capable design. Performance requirements must be met strictly by debugging timing paths while synthesizing & routing the design. Knowledge and ability to alter the design is required to complete the stages of synthesis and to ensure a logically equivalent design with correct metrics for power consumption, timing delays, and optimization.

Responsible for developing and executing software test plans, debuging, and analyzing test results to ensure correct functionality of complicated IPs within a system on chip. Worked on the Atom processor and numerous Intel server CPUs. Routinely determined the root causes of failures within circuitry or software and recommended design solutions. Software scripts were developed in Python to test the processors. Validation engineers require a deep understanding of complex computer architecture to effectively debug and validate the intended functionality of the chipset. Extensive communication with the chip designers and architects was necessary.