Omkar Chavare Email & Phone Number

Good knowledge of digital ciruit design, computer architecture, ADC architecure, static timing analysis, clockgating, clock domain crossing, power analysis of high performance, mixed-signal IPs in advanced finFETtechnology nodes.• Hands-on experience in RTL coding, verification using system verilog based testcases, Lint checks,writing design constraint files for IP which include timing constraints, false and multi-cycle pathinformation, CDC/RDC checks, removing timing violation (STA) and DFT violations .• Hands-on experience in creating waiver files for timing/DFT/CDC/RDC/code coverage.• Good RTL and GATE level simulation Debug skills.• Proficient in sccripting languages Tcl and shell.