Onur Ucler Email and Phone Number

Reference Manageability Firmware Development:◦ Led the development of reference manageability firmware for CubeSat.◦ Implemented SOSA Tier3/VITA Specifications Compliance reference firmware.◦ Developed Intelligent Platform Management Interface (IPMI) firmware for Out of Band (OOB) communication between SOSA Modules in C.◦ Coded Intelligent Platform Management Bus (IPMB) firmware for message transmission using I2C protocol in C.Chassis/System Manager Firmware Engineering:◦ Engineered Chassis/System Manager firmware for monitoring and controlling SOSA Compliance.◦ Monitored Current (I), Voltage (V), and Temperature (T) on each SOSA module through UART interface.◦ Configured IVT settings on the system and controlled Power Rails.Integration Across SOSA Modules:◦ Integrated code across diverse SOSA modules.Collaboration with Teams:◦ Collaborated with internal hardware design teams to define hardware specs and provided valuable feedback.◦ Contributed to SOSA and VITA specifications.Firmware Deployment:◦ Deployed firmware to customers, ensuring seamless integration with customer hardware.◦ Provided a static API and binaries for ease of implementation.◦ Released a user guide covering firmware details, hardware setup, and flashing using JTAG/SWD.

Development in Python:◦ Developed proprietary technical indicators using Deep Leaning Models.◦ Designed and implemented a stock scanning tool for identifying up/down trending stocks using AI methodologies.◦ Created plotting tools for visualizing stock actions through technical analysis.◦ Implemented a RESTful API interface to facilitate interaction with the tool.◦ Developed a trading strategy finder using Reinforcement Learning.Product Deployment:◦ Released the scanning and charting capabilities of the tool on the Slack platform.

AI System Development:◦ Led development of an AI system for generating video solutions to math questions.◦ Implemented a transformer model math question classifier in PyTorch.◦ Developed a Flash RESTful API interface to handle incoming requests.◦ Created a Python tool for generating dynamic video responses with voice for math questions.Global Team Management:◦ Managed a global team with a focus on implementing a custom Agile methodology using Jira.◦ Conducted interviews, hired resources, and provided mentorship on processes, vision, and AI.• Funding Management:◦ Orchestrated funding efforts, including setting up meetings with investors, presenting the company's vision, and crafting a comprehensive business plan.◦ Prepared and delivered compelling pitch decks to secure financial support.Product Deployment: ◦ Successfully deployed the product to customers, overseeing the release of alpha and beta versions for iOS, Android apps, and a website.◦ Conducted A/B testing for version releases, ensuring optimal performance and user experience.◦ Collected and analyzed user feedback to inform iterative improvements for subsequent releases.

Development in C++/Python:◦ Developed Power Management tools for 10nm x86 Intel architecture PCH chipsets using the LLVM framework.◦ Architected a framework for Power States, Core States, Performance States, and Sleep States for 10nm x86 PCH chipsets within a custom LLVM framework.◦ Implemented a tool utilizing RNN Deep Learning Models to reduce redundant coding.Collaboration:◦ Led the development of power management tools across sites, overseeing a team of 10 developers.◦ Trained the internal team on the implementation of architecture and development guidelines.◦ Collaborated with the validation team to enable debug tools, address issues, and incorporate feedback from customers.◦ Worked closely with other architecture teams to synchronize efforts towards the overall goal.Methodology:◦ Followed Agile development methodology.◦ Maintained daily synchronization, planned bi-weekly, and conducted quarterly reflections.Deployment:◦ Released user guide and provided training how to use it globally. ◦ Produced a comprehensive user guide and conducted training sessions for global usage.

IP Ownership:◦ Led Firmware Development for the Converged Security Manageability Engine (CSME) IP.Development in C++:◦ Developed and implemented Power Management and Reset sequence tests to validate the CSME IP using the LLVM framework.Deployment:◦ Globally released the validation tool for use by other teams.Collaboration and Firmware Enablement:◦ Collaborated closely with the validation team to enable the firmware on a variety of x86 architecture products: Haswell (22nm), Broadwell (14nm), and Skylake (14nm).◦ Worked collaboratively with the validation team to enable debug tools, address issues, and incorporate feedback from customers.Mentorship and Training:◦ Provided mentorship to new team members.◦ Conducted training sessions on firmware enablement and usage for other teams. Methodology:◦ Followed Agile development methodology.◦ Maintained daily synchronization, planned bi-weekly, and conducted quarterly reflections.

IP Ownership:◦ Led Post-Si validation efforts for PCIe IP.Development and Testing:◦ Designed and implemented a comprehensive test plan for PCIe, covering Link States, Gen1/2/3 Speed, Wake from Sleep State, and concurrency with other traffic.◦ Developed a Python tool to validate Sleep Sx state entry/exit.Deployment and Execution/Debug:◦ Released a detailed PCIe validation plan.◦ Executed the PCIe plan, actively identifying and resolving issues.◦ Collaborated closely with the hardware design team to address hardware bugs.. Collaboration and Communication:◦ Collaborated with hardware developers to provide bug fixes.◦ Worked daily with technicians to set up test cases based on the test plan.◦ Presented regular status updates to upper management.Methodology:◦ Followed Agile development methodology.◦ Maintained daily synchronization, planned bi-weekly, and conducted quarterly reflections.

• Definition: Collaborating with design engineers to identify challenges or blocking issues and came up with software resolutions that eliminate those blocks. The team worked in a custom SRAM design and accurate timing measurements were crucial. Chiefly, provided timing and ecosystem related software solutions were provided.• General Tasks: Software solutions for Static Timing Analysis (STA) and developing ecosystem for design work environment. • Software Language Used: Python, Perl, Tcl, and C#.

• Responsibilities: RTL and circuit design of DDR3 module. • Assigned Features: Circuit and RTL Design. • Gained Skills: Knowledge of Circuit and RTL design, and DDR3 architecture. • Utilized Tools: System Verilog Language and Circuit simulator tools.

• Responsibilities: Taught the fundamentals of embedded systems and digital electronics. • Thought Classes: Embedded Microcontroller and Digital Fundamentals.• Gained Skills: C, Verilog, and VHDL Language Programming; Architecture of AVR Mega16, FPGA design. • Utilized Tools: Logic Analyzer, Oscilloscope, Quartus II, Multusim.