Digital IC Design and Verification TrackThe training gives expertise in digital design flow for ASIC including Verilog modelling, synthesis, minimization, standard-cell libraries, timing optimization, timing models, timing analysis & constraints, Clock Tree Synthesis, placement and routing, Signoff and chip finishing, and design for testing. Regarding the verification and testing of digital systems, the SystemVerilog concepts such as Data types, Function, threads, Interfaces, randomization, Code Coverage, Functional Coverage and Assertion Based Verification are covered. In addition to OOP and Hierarchal Testbenchs. UVM verification projects including components such as transaction, generator, configuration, sequencer, driver, monitor, …. also, faults in digital systems, test generation and testable systems, and pattern generation and comparator circuits of the built-in-self-test. In addition, the VLSI and full custom IC design flow topics learned include design of complex digital circuits, PLA, Arithmetic Blocks, Memory Design, system interconnect, Clock Generators and System Level Integration and it is emphasizing principles such as power optimization, timing analysis, and signal and power integrity issues. These modules are delivered by worldwide industry experts and university professors. Through hands-on experience in the labs with industry-standard CAD tools.CAD tools include: Synopsys’s flow (Design Compiler, Formality, Library Manager, ICC2, PrimeTime, VCS, Verdi), Siemens’s flow (Tanner EDA: S-Edit, L-Edit, W-Edit, Calibre), Questa, Intel’s Quartus, and Cadence Virtuoso.Languages: SystemVerilog, Verilog