Michael Pakes Email & Phone Number

Raleigh-Durham, North Carolina Area

Providing FPGA contract services to supplement existing team on a new project.

Looking for next opportunity as a FPGA Designer.

Richardson, Texas

Ethernet centric FPGA design for Enterprise carrier and back-haul applications. FPGA design experience included Layer 2 and 3 packet classification, Class of Service (CoS) level packet policing, SOAM Delay Measurement, Ethernet tag operations for untagged and multi-tagged packets, RFC2544 packet monitoring, and packet synchronization over Carrier Ethernet.

Richardson, Texas

Supported Xilinx FPGAs exclusively.Multiphase support; initial sales call, system architecture design, device implementation, customer technical assistance, and development tools support.Functioned in a multitasking environment demanding excellent communication and organizational skills to provide dynamic support for simultaneous customer.

Plano, Texas

Developed a large embedded processor design using Altera's System on a Programmable Chip (SOPC) development tool suite. Incorporated dual soft-core processors, supporting peripherals, and two independent Triple-Speed Ethernet MACs.

Richardson, Texas

6 month FPGA contract to design new product to facilitate transport of T1 and Ethernet traffic over unchannelized T3.

Plano, Texas

Developed SONET OC-48 Section and Line termination FPGA designs.

Plano, Texas

Initially supported T1/T3 module redesigns of existing equipment. Transitioned to designing SONET STS-1 circuits for a new multirate cross-connect. In 1995 I developed an extensive testbench in VHDL to support STS-1 inbound data path testing. I designed with FPGAs from 1995 on implementing SONET OC-3, OC-12, and OC-48 circuits.

Grand Prairie, Texas

Designed guidance computers for missile programs.High-speed digital designs were implemented in CPLDs to interface dual 68040 processors, a Weitek floating-point coprocessor as well as various peripheral interface devices.