Palkesh Jain
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Palkesh Jain Email & Phone Number

Senior Director, Technology, at Qualcomm at Qualcomm
Location: Bengaluru, Karnataka, India 7 work roles 3 schools
1 work email found @qualcomm.com LinkedIn matched
✓ Verified July 2026 4 data sources Profile completeness 100%

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Current company
Role
Senior Director, Technology, at Qualcomm
Location
Bengaluru, Karnataka, India
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Who is Palkesh Jain? Overview

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Quick answer

Palkesh Jain is listed as Senior Director, Technology, at Qualcomm at Qualcomm, a with 37431 employees, based in Bengaluru, Karnataka, India. AeroLeads shows a work email signal at qualcomm.com and a matched LinkedIn profile for Palkesh Jain.

Palkesh Jain previously worked as Senior Director of Technology at Qualcomm and Principal Engineer at Qualcomm. Palkesh Jain holds Doctor Of Philosophy - Phd, Computer Science, Cum Laude from Universitat Politècnica De Catalunya.

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Email format at Qualcomm

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{first_initial}{last}@qualcomm.com
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Profile bio

About Palkesh Jain

Palkesh Jain is a Senior Director, Technology, at Qualcomm at Qualcomm. He possess expertise in soc, semiconductors, cmos, reliability, ic and 21 more skills.

Listed skills include Soc, Semiconductors, Cmos, Reliability, and 22 others.

Current workplace

Palkesh Jain's current company

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Qualcomm
Qualcomm
Senior Director, Technology, at Qualcomm
san diego, california, united states
Website
Employees
37431
AeroLeads page
7 roles

Palkesh Jain work experience

A career timeline built from the work history available for this profile.

Senior Director Of Technology

Current

Greater Bengaluru Area

Working across various teams and delivering solutions at chip/system/package level to alleviate thermal and PDN challenges. Leading the team to develop advanced and innovative design techniques / algorithms to help improve design Vmin, limited by PDN, thermal and reliability effects. Understanding and exploiting the package/system level knobs for pushing the performance envelope of benchmarks as well as power gains.

Oct 2022 - Present

Principal Engineer

Bangalore

Working on design methodologies at chip and system level to alleviate thermal and PDN challenges. Leading the team to develop advanced and innovative design techniques / algorithms to help improve design Vmin, limited by PDN, thermal and reliability effects.

Sep 2018 - Nov 2022

Sr. Staff Engineer

Bangalore

Working on design methodologies at chip and system level to alleviate thermal and PDN challenges. Leading the team to develop advanced and innovative design techniques / algorithms to help improve design Vmin, limited by PDN, thermal and reliability effects.

Sep 2014 - Sep 2018

Technologist

Leading the team (of 6) to define, develop and deploy CAD-methodology solutions to solve the design-reliability and power-integrity problems of IPs and SoC. Offering leading edge solutions on problems like Electromigration, Transistor Reliability (Gate oxide damage, hot-carriers, NBTI, plasma charging damage), Electro-static discharge (ESD) and IR drop (static; dynamic and rampup). The work encompasses, in breadths and depths, the fields of transistor, interconnects, circuit & SoC reliabiltiy, SoC leakage and variability.

Jan 2012 - Sep 2014

Reliability And Power-Integrity Solutions Leader

Working on defining, developing and deploying reliability/power-integrity solutions across different Business Units within TI.

Feb 2011 - Jan 2012

Reliability Lead

Working as Reliability Lead to consult and solve design reliability issues at advanced technology node.

Nov 2009 - Feb 2011

Senior Design Engineer - Design Reliability And Integrity Expert

Designed, developed and deployed solutions to address the problem of design reliability and integrity design of IPs and SoC. The profile gave deep vertical and horizontal opportunities to solve the problem space holisitically through design CAD, semiconductor device physics, circuits, methods and SoC design practices, substantiated by numerous patents and external publications in reputed journals and conferences.The work encompasses, in breadths and depths, the fields of transistor, interconnects, circuit & SoC reliabiltiy, SoC leakage and variability.

Jul 2004 - Nov 2009
Team & coworkers

Colleagues at Qualcomm

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3 education records

Palkesh Jain education

Doctor Of Philosophy - Phd, Computer Science, Cum Laude

The research dealt with faster and efficient algorithms for reliability analysis of semiconductor systems, more so with redundancy. Guided.

Bachelors And Masters, Electrical Engineering

Activities and Societies: IEEE member, since 2001 Recieved the Bachelors and Masters in EE from IIT Bombay as part of the five year dual.

Education record

St. Pauls School Indore
FAQ

Frequently asked questions about Palkesh Jain

Quick answers generated from the profile data available on this page.

What company does Palkesh Jain work for?

Palkesh Jain works for Qualcomm.

What is Palkesh Jain's role at Qualcomm?

Palkesh Jain is listed as Senior Director, Technology, at Qualcomm at Qualcomm.

What is Palkesh Jain's email address?

AeroLeads has found 1 work email signal at @qualcomm.com for Palkesh Jain at Qualcomm.

Where is Palkesh Jain based?

Palkesh Jain is based in Bengaluru, Karnataka, India while working with Qualcomm.

What companies has Palkesh Jain worked for?

Palkesh Jain has worked for Qualcomm and Texas Instruments.

Who are Palkesh Jain's colleagues at Qualcomm?

Palkesh Jain's colleagues at Qualcomm include Tom Teng, Sharon Corwin, Aaron Jones, Aditi ., and Sean (Xuyang) Zhou.

How can I contact Palkesh Jain?

You can use AeroLeads to view verified contact signals for Palkesh Jain at Qualcomm, including work email, phone, and LinkedIn data when available.

What schools did Palkesh Jain attend?

Palkesh Jain holds Doctor Of Philosophy - Phd, Computer Science, Cum Laude from Universitat Politècnica De Catalunya.

What skills is Palkesh Jain known for?

Palkesh Jain is listed with skills including Soc, Semiconductors, Cmos, Reliability, Ic, Vlsi, Asic, and Mixed Signal.

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