Palkesh Jain Email and Phone Number

Working across various teams and delivering solutions at chip/system/package level to alleviate thermal and PDN challenges. Leading the team to develop advanced and innovative design techniques / algorithms to help improve design Vmin, limited by PDN, thermal and reliability effects. Understanding and exploiting the package/system level knobs for pushing the performance envelope of benchmarks as well as power gains.

Working on design methodologies at chip and system level to alleviate thermal and PDN challenges. Leading the team to develop advanced and innovative design techniques / algorithms to help improve design Vmin, limited by PDN, thermal and reliability effects.

Working on design methodologies at chip and system level to alleviate thermal and PDN challenges. Leading the team to develop advanced and innovative design techniques / algorithms to help improve design Vmin, limited by PDN, thermal and reliability effects.

Leading the team (of 6) to define, develop and deploy CAD-methodology solutions to solve the design-reliability and power-integrity problems of IPs and SoC. Offering leading edge solutions on problems like Electromigration, Transistor Reliability (Gate oxide damage, hot-carriers, NBTI, plasma charging damage), Electro-static discharge (ESD) and IR drop (static; dynamic and rampup). The work encompasses, in breadths and depths, the fields of transistor, interconnects, circuit & SoC reliabiltiy, SoC leakage and variability.

Working on defining, developing and deploying reliability/power-integrity solutions across different Business Units within TI.

Working as Reliability Lead to consult and solve design reliability issues at advanced technology node.

Designed, developed and deployed solutions to address the problem of design reliability and integrity design of IPs and SoC. The profile gave deep vertical and horizontal opportunities to solve the problem space holisitically through design CAD, semiconductor device physics, circuits, methods and SoC design practices, substantiated by numerous patents and external publications in reputed journals and conferences.The work encompasses, in breadths and depths, the fields of transistor, interconnects, circuit & SoC reliabiltiy, SoC leakage and variability.