Pankaj Baghmar Email & Phone Number

Munich, Bavaria, Germany

Spain

• I am responsible for Top and block level Physical design backend implementation.I was also managing and training others. I have experience in PNR (Place and route), Signoff (LVS,ERC,DRC,EM,IR,Antenna etc) Floorplan.
• Primary Skills: Synthesis to GDSPNR, Worked in TOP and Block level. Parasitic Extraction, Running EM/IR,Post Layout timing closure and Sign off (LVS,DRC,ERC,IR,Antenna,etc)
• Scripting: Good knowledge of shell, Perl, Tcl scripting
• Timing: Strong background in STA closure
• Technologies Node: 5nm,7nm, 16nm,14nm, 55nm
• Foundry: TSMC, samsung, UMC

Bengaluru, Karnataka, India

• I worked here for more than 4 year. I was responsible for block level PNR(Place and route) and sign off (STA,ERC,DRC,Antenna,LEC etc). I worked in multiple tape outs for AMD,Mediatek,ARM.
• Project 7 (Mediatek Ethernet): Responsible for Complete PnR, Timing Closure, Logical and Physical Verification & sign off.Frequency 1GHZ, 3M instance, 424 srams,7nm Technology.PNR in ICC2.Low power design.
• Project 8 (Mediatek Mobile SOC): Responsible for Complete PnR, Timing Closure, Logical and Physical Verification & sign off.Frequency 0.54 GHZ, 2.6M instance, 80 srams, 7nm Technology. PNR in INNOVUS. Low power Design.
• Project9 (AMD Graphics processor):Responsible for Complete PnR, Timing Closure, Logical and Physical Verification & sign off for multiple block. Sram dominated design.7nm Technology,PNR in ICC2.High Operating frequency.
• Project10 (ARM graphics processor): Responsible for Complete PnR, Timing Closure & sign off. Frequency - 500Mhz Tool Used: ICC2
• Primary Skills: Synthesis to GDSPNR, Worked in TOP and Block level. Parasitic Extraction, Running EM/IR,Post Layout timing closure and Sign off (LVS,DRC,ERC,IR,Antenna,etc)

Bachelor Of Technology - Btech, Electrical, Electronics And Communications Engineering

Higher Secondary, Physics Chemistry Maths

Bachelor'S Degree, Electronics And Communication Engineering