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Parag Salve phone numbers
Parag Salve is a Co-founder and COO at Thalmaar. He possess expertise in verilog, testing, perl, simulations, analog circuit design and 16 more skills. Colleagues describe him as "I worked with Parag for close to 3 years including in capacity of Manager and it was great working with him. Parag is passionate, enthusiastic and professional about his work. He is curious and likes challenges. It was a great pleasure working alongside with him on numerous projects" and "In the 2.5 years that I have worked with Parag, I have found him to be extremely professional and highly competent in test software development. Parag has a tremendous work ethic and is a great team player who is willing to do whatever it takes to help the company succeed. I strongly recommend Parag."
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Co-Founder And CooThalmaarLos Angeles, Ca, Us -
Founder & CeoSalventuretech Sep 2014 - PresentSalventure.tech (Formerly SalveSoft) established in 2014 is an ISO 9001:2015 certified Engineering outperformer. We have carved a strong niche in the field of Industrial IoT. SalventureTech is a mid-sized engineering-centric team powered by young, passionate, ‘Data-Centric’ individuals having rich and varied experience. Coupled with a skilled, motivated employee base and capacity to grow at maximum our focus is to grow and provide qualitative, timely, and smart solutions to our customers worldwide. -
Lead AteEmpower Rf Systems May 2020 - Mar 2023Inglewood, Ca, Us• Lead test team for ATE production testing of RF L-Band, S-Band, and C-Band Defense equipment. • UVM and verification/validation requirements fulfilled using C++ and System Verilog. • Automation development and post-processing in Python. • Utilize JTAG debuggers and toolchains for JTAG responsibilities. • Create test plans and procedures for Pre-Si and Post-Si validation including development and characterization. • Collaborate with the design team for RTL designs and characterization feedback. • Extensive use of NI PXI instrument for usage, SCPI communication, and automation with VNA, Oscilloscope, Signal Generator among other PXI-based instruments. -
Test Team LeadWet (Design) Apr 2019 - May 2020Us• Leading test team for automation and electrical test requirements of production lines and product development.• Firmware development and post processing in Python and C++. • Automation in LabView for Production lines with opto electrical setups and sensors. • Lead, develop, implement test plan, procedures and reports for testing efforts on HV and LV products -
Hardware EngineerGoogle Life Sciences (Verily) Mar 2018 - Mar 2019•Responsible for PCBA and Device ATE for class III Neuromodulation device.•Responsible for Vendor management, Hardware and Software ATE development.•Python automation at PCBA and Device ATE levels with revision control using Git, Gerrit and Sourcetree•Understand the test requirements, architecture and handle the efforts for hardware testing with NI ATE test equipment.•Extensive usage of NI ATE equipment (SMU, DAQ) as well as lab equipment like oscilloscope, power supplies and DAQ.•Qual (HTOL, UHAST, TCT, HTS, THB) tests performed.
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Senior Test Development EngineerMrv Communications Jul 2014 - Jan 2018Chatsworth, Ca, Us•Responsible for product management, knowledge transfer and smooth transitioning for manufacturing of MRV products (High Speed Networking Solutions) to International and local vendors. • MRV products include Optical-Electrical-Optical switches, Optical transport solution at 10GBPS, 100GBPS and 200GBPS. Extensive experience with multi-slot chassis, distributed chassis, chassis management, redundancy via Ethernet/IP wireless communication. • Production line automation using Perl, Tcl, C, C++ and Python. • Responsible for JTAG and Boundary Scan capabilities and its utilization on MRV products. • Creating Test Procedures and Plans along the lines of DFT and DFM. • CVI GUI creations, Perl and Tcl Automation for Production Testing.• Extensive Perl scripting for automating tests on complex fiber optic communication modules having more than 80,000 routes. •Script generations and usage for fixing bugs on complex fiber optic communication modules. -
Co-FounderCall-A-Mechanic Sep 2015 - Dec 2016https://www.facebook.com/callamechanic.nagpur
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Hardware Design Engineer At St Jude R&DSt. Jude Medical Cardiac Rhythm Med Division May 2009 - Jul 2014St. Paul, Minnesota, Us• ATE Test Developer: Developing test suites for testing ASICs and Back-annotating gate level netlists of major blocks in Digital and Memory sections of a pacemaker and an ICD. C++ used for code development on D10 Credence/Advantest testers. System Verilog (OVM/VMM) was also used for testbench creation. • MEMORY Verification and Characterization: Testing and characterization (on multiple voltages, timing, frequency, and temperature) of memory modules (FRAM, SRAM, ROM) of varying sizes (2MB to 8MB) using various rigorous algorithms developed in SystemVerilog and hex codes. Vector files from these algorithms were run on ATE testers. • Automation software Developer: Designed and developed in-house softwares for automation using C++, Perl, and VBA. Tasks include integrating and automating various Tektronix and Agilent instruments using LabView and developing statistical analysis techniques for evaluating test benches results using MSA.• RTL Developer: Developing verilog RTL by understanding the physiological aspect behind the function and therapies of pacemaker and ICDs. Also assisted in the characterization and verification of ICDs and implantable pacemakers.• Efficiently lead multiple teams on successfully reviewing and qualifying an Alternate Substrate Source for pacemakers and ICDs. Product cost reduction was achieved via extensive evaluation of alternative components with statistical tools. • Extensive hands on experience on ATE Testers (LTX-Credence D10) and lab equipments such as , Oscilloscopes, Function Analyzers, Bread boards etc.* Extensive Test plan, procedure and report creation for each module at both system as well as at chip levels. -
Test Engineer (Contract)St. Jude Medical Cardiac Rhythm Med Division Feb 2009 - May 2009St. Paul, Minnesota, Us• Characterization and data collection of MEMS and Kynar sensor.• Temperature variation measurements for Timebase oscillators. Data was processed using excel and VBA macros.• Data processing and mining out of huge ATE datalog files using Perl. -
Verification InternCadence Design Systems May 2008 - Jul 2008San Jose, California, Uso Was involved in Testing and Verification of C2Silicon Software of Cadence Inc, Milpitas San Jose. o Involved in testing of Verilog output for an Input in C, C++ and SystemC.o Graphical User Interface (GUI) of the software was tested using Perl and Tcl.o Recording of events which are to be released with the user guide of the software.
Parag Salve Skills
Parag Salve Education Details
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University Of Southern CaliforniaDigital Vlsi -
Shri Ramdeobaba College Of Engineering And ManagementElectrical And Electronics Engineering -
Somalwar Academy Education SocietyHigh School
Frequently Asked Questions about Parag Salve
What company does Parag Salve work for?
Parag Salve works for Thalmaar
What is Parag Salve's role at the current company?
Parag Salve's current role is Co-founder and COO.
What is Parag Salve's email address?
Parag Salve's email address is ps****@****ign.com
What is Parag Salve's direct phone number?
Parag Salve's direct phone number is +121322*****
What schools did Parag Salve attend?
Parag Salve attended University Of Southern California, Shri Ramdeobaba College Of Engineering And Management, Somalwar Academy Education Society.
What are some of Parag Salve's interests?
Parag Salve has interest in Investing, Yoga, Film Making, Racquetball, Cricket, Invention And Entrepreneur Engineering, Animation(Blender).
What skills is Parag Salve known for?
Parag Salve has skills like Verilog, Testing, Perl, Simulations, Analog Circuit Design, Python, Medical Devices, Matlab, Tcl, Characterization, C++, Embedded Systems.
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