Parag Salve Email & Phone Number
@wetdesign.com
4 phones found area 213, 989, and 800
LinkedIn matched
Who is Parag Salve? Overview
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Parag Salve is listed as Co-founder and COO at Thalmaar, based in Nagpur, Maharashtra, India. AeroLeads shows a work email signal at wetdesign.com, phone signal with area code 213, 989, 800, and a matched LinkedIn profile for Parag Salve.
Parag Salve previously worked as Founder & CEO at Salventuretech and Lead ATE at Empower Rf Systems. Parag Salve holds Master'S Degree, Digital Vlsi from University Of Southern California.
Email format at Thalmaar
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AeroLeads found 1 current-domain work email signal for Parag Salve. Compare company email patterns before reaching out.
About Parag Salve
Parag Salve is a Co-founder and COO at Thalmaar. He possess expertise in verilog, testing, perl, simulations, analog circuit design and 16 more skills. Colleagues describe him as "I worked with Parag for close to 3 years including in capacity of Manager and it was great working with him. Parag is passionate, enthusiastic and professional about his work. He is curious and likes challenges. It was a great pleasure working alongside with him on numerous projects" and "In the 2.5 years that I have worked with Parag, I have found him to be extremely professional and highly competent in test software development. Parag has a tremendous work ethic and is a great team player who is willing to do whatever it takes to help the company succeed. I strongly recommend Parag."
Listed skills include Verilog, Testing, Perl, Simulations, and 17 others.
Parag Salve's current company
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Parag Salve work experience
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Founder & Ceo
CurrentSalventure.tech (Formerly SalveSoft) established in 2014 is an ISO 9001:2015 certified Engineering outperformer. We have carved a strong niche in the field of Industrial IoT. SalventureTech is a mid-sized engineering-centric team powered by young, passionate, ‘Data-Centric’ individuals having rich and varied experience. Coupled with a skilled, motivated.
Lead Ate
- Lead test team for ATE production testing of RF L-Band, S-Band, and C-Band Defense equipment.
- UVM and verification/validation requirements fulfilled using C++ and System Verilog.
- Automation development and post-processing in Python.
- Utilize JTAG debuggers and toolchains for JTAG responsibilities.
- Create test plans and procedures for Pre-Si and Post-Si validation including development and characterization.
- Collaborate with the design team for RTL designs and characterization feedback.
Test Team Lead
- Leading test team for automation and electrical test requirements of production lines and product development.
- Firmware development and post processing in Python and C++.
- Automation in LabView for Production lines with opto electrical setups and sensors.
- Lead, develop, implement test plan, procedures and reports for testing efforts on HV and LV products
Hardware Engineer
- Responsible for PCBA and Device ATE for class III Neuromodulation device.
- Responsible for Vendor management, Hardware and Software ATE development.
- Python automation at PCBA and Device ATE levels with revision control using Git, Gerrit and Sourcetree
- Understand the test requirements, architecture and handle the efforts for hardware testing with NI ATE test equipment.
- Extensive usage of NI ATE equipment (SMU, DAQ) as well as lab equipment like oscilloscope, power supplies and DAQ.
- Qual (HTOL, UHAST, TCT, HTS, THB) tests performed.
Senior Test Development Engineer
- Responsible for product management, knowledge transfer and smooth transitioning for manufacturing of MRV products (High Speed Networking Solutions) to International and local vendors.
- MRV products include Optical-Electrical-Optical switches, Optical transport solution at 10GBPS, 100GBPS and 200GBPS. Extensive experience with multi-slot chassis, distributed chassis, chassis management, redundancy via.
- Production line automation using Perl, Tcl, C, C++ and Python.
- Responsible for JTAG and Boundary Scan capabilities and its utilization on MRV products.
- Creating Test Procedures and Plans along the lines of DFT and DFM.
- CVI GUI creations, Perl and Tcl Automation for Production Testing.
Co-Founder
https://www.facebook.com/callamechanic.nagpur
Hardware Design Engineer At St Jude R&D
- ATE Test Developer: Developing test suites for testing ASICs and Back-annotating gate level netlists of major blocks in Digital and Memory sections of a pacemaker and an ICD. C++ used for code development on D10.
- MEMORY Verification and Characterization: Testing and characterization (on multiple voltages, timing, frequency, and temperature) of memory modules (FRAM, SRAM, ROM) of varying sizes (2MB to 8MB) using various rigorous.
- Automation software Developer: Designed and developed in-house softwares for automation using C++, Perl, and VBA. Tasks include integrating and automating various Tektronix and Agilent instruments using LabView and.
- RTL Developer: Developing verilog RTL by understanding the physiological aspect behind the function and therapies of pacemaker and ICDs. Also assisted in the characterization and verification of ICDs and implantable.
- Efficiently lead multiple teams on successfully reviewing and qualifying an Alternate Substrate Source for pacemakers and ICDs. Product cost reduction was achieved via extensive evaluation of alternative components.
- Extensive hands on experience on ATE Testers (LTX-Credence D10) and lab equipments such as, Oscilloscopes, Function Analyzers, Bread boards etc.* Extensive Test plan, procedure and report creation for each module at.
Test Engineer (Contract)
- Characterization and data collection of MEMS and Kynar sensor.
- Temperature variation measurements for Timebase oscillators. Data was processed using excel and VBA macros.
- Data processing and mining out of huge ATE datalog files using Perl.
Verification Intern
o Was involved in Testing and Verification of C2Silicon Software of Cadence Inc, Milpitas San Jose. o Involved in testing of Verilog output for an Input in C, C++ and SystemC.o Graphical User Interface (GUI) of the software was tested using Perl and Tcl.o Recording of events which are to be released with the user guide of the software.
Parag Salve education
Master'S Degree, Digital Vlsi
Engineer'S Degree, Electrical And Electronics Engineering
High School
Frequently asked questions about Parag Salve
Quick answers generated from the profile data available on this page.
What company does Parag Salve work for?
Parag Salve works for Thalmaar.
What is Parag Salve's role at Thalmaar?
Parag Salve is listed as Co-founder and COO at Thalmaar.
What is Parag Salve's email address?
AeroLeads has found 1 work email signal at @wetdesign.com for Parag Salve at Thalmaar.
What is Parag Salve's phone number?
AeroLeads has found 4 phone signal(s) with area code 213, 989, 800 for Parag Salve at Thalmaar.
Where is Parag Salve based?
Parag Salve is based in Nagpur, Maharashtra, India while working with Thalmaar.
What companies has Parag Salve worked for?
Parag Salve has worked for Thalmaar, Salventuretech, Empower Rf Systems, Wet (Design), and Google Life Sciences (Verily).
How can I contact Parag Salve?
You can use AeroLeads to view verified contact signals for Parag Salve at Thalmaar, including work email, phone, and LinkedIn data when available.
What schools did Parag Salve attend?
Parag Salve holds Master'S Degree, Digital Vlsi from University Of Southern California.
What skills is Parag Salve known for?
Parag Salve is listed with skills including Verilog, Testing, Perl, Simulations, Analog Circuit Design, Python, Medical Devices, and Matlab.
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