Parth Zaveri Email & Phone Number

Bengaluru, Ka, In

Bengaluru, Karnataka

Bengaluru Area, India

• Integrated the Synopsys Model (VIP) for various different projects.• Generated the Power vectors for the analysis of maximum Bandwidth utilization on different projects.• Reported bugs found in the design (Jiras) and effectively collaborated with the Designers to address the failures.• Generated the functional coverage analysis for the above modules by defining SystemVerilog assertions and covergroups.• Debugged Miscellaneous connectivity and Interrupt testcase scenarios.

Bengaluru Area, India

Gangnam-Gu, Seoul, Korea

Bengaluru Area, India

• Currently working on the Soc level Verification of the System Level Cache (SLC) module.

Chandler

• Headed the IP Verification of UART-Smartcard and AFE-Current Bias modules at unit level.• Created the verification requirements in the Freeplan tool based on the specification in the DOS.• Teamed with Architects and Designers to create the testplans. • Developed the unit level testcases for the above modules.• Filed bug reports (Jiras) and verified RTL fixes.• Developed scoreboard, monitors, sequencers and scenarios in VMM-based verification methodology to setup the testbench environment using System Verilog.• Constantly updated the environment components to support verification of new features being added in the design.• Performed the functional coverage analysis for modules by defining SystemVerilog assertions and covergroups.• Developed test-cases for integrating the (MCCP) modules at full-chip level.

San Francisco Bay Area

• Developed Perl Script for generating macros library using verilog files.• Developed TCL scripts to automate the EDA tool to compile and PNR the SOC designs.

San Francisco Bay Area

• Maintain administrative office tasks such as filing, running errands, data entry and computing.• Compiling Student grades into MS Excel spreed sheets for reporting purpose and deriving class statistics from the data.• Providing Audio/video support for lectures and class related events.

San Francisco Bay Area

Completed the Masters Program in Electrical Engineering at San Jose State University.

Sunnyvale California

Primarily develop software and test PCB’s for a custom mixed-signal ASIC. Develop modules for communication with the microprocessor over UART, SPI, I2C, and DALI.Develop a state machine controller for an RF powered plasma lamp based on the RTX RTOS for ARM Cortex-M0 microcontroller. Day-to-day responsibilities such as software design, coding, and documentation, as well as PCB schematic generation.

Masters, Electrical Engineering

Bachelor Of Engineering, Electronics

Diploma, Indusrial Electronics

Secondary School Certificate

Activities and Societies: Passed the Offcial exam of Elementary Grade Drawing Examination held by the Government of Maharashtra. Actively.