Parth Zaveri

Parth Zaveri Email and Phone Number

Senior Staff Engineer @ Qualcomm
Bengaluru, KA, IN
Parth Zaveri's Location
Bengaluru, Karnataka, India, India
About Parth Zaveri

• Experience of RTL coding, synthesis, and verification using Verilog.• Proficient at test benches creation.• Knowledge of designing and implementing State machines of Digital Systems.• Knowledge of Static Timing analysis, False path in STA, Timing optimization.Seeking an Full-time position with a company that would allow me to apply and enhance the above skills in Electrical Engineering with emphasis in VLSI circuits designing.Specialties: Programming languages: C, Verilog, VHDL, Perl, Assembly Languages.Tools: VCS, Pspice, Design Vision, Microwind, Modelsim, Matlab, Xilinx ISE, Labview, Microsoft Office. Operating systems: Windows XP/Vista/Windows7, Linux.Electronic tools: Multimeter, Oscilloscope, Voltmeter, Frequency Generator and Counter.

Parth Zaveri's Current Company Details
Qualcomm

Qualcomm

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Senior Staff Engineer
Bengaluru, KA, IN
Website:
qualcomm.com
Employees:
48952
Parth Zaveri Work Experience Details
  • Qualcomm
    Senior Staff Engineer
    Qualcomm
    Bengaluru, Ka, In
  • Cadence Design Systems
    Principal Design Engineer
    Cadence Design Systems Apr 2020 - Present
    Bengaluru, Karnataka
  • Qualcomm
    Senior Verification Engineer
    Qualcomm Nov 2017 - Mar 2020
    Bengaluru Area, India
    • Integrated the Synopsys Model (VIP) for various different projects.• Generated the Power vectors for the analysis of maximum Bandwidth utilization on different projects.• Reported bugs found in the design (Jiras) and effectively collaborated with the Designers to address the failures.• Generated the functional coverage analysis for the above modules by defining SystemVerilog assertions and covergroups.• Debugged Miscellaneous connectivity and Interrupt testcase scenarios.
  • Sevitech Systems Pvt. Ltd.
    Senior Verification Engineer
    Sevitech Systems Pvt. Ltd. Nov 2016 - Mar 2020
    Bengaluru Area, India
  • Silicon Works
    Senior Verification Engineer
    Silicon Works Apr 2017 - Oct 2017
    Gangnam-Gu, Seoul, Korea
  • Lg Soft India
    Senior Verification Engineer
    Lg Soft India Nov 2016 - Mar 2017
    Bengaluru Area, India
    • Currently working on the Soc level Verification of the System Level Cache (SLC) module.
  • Microchip Technology
    Verification Engineer
    Microchip Technology Mar 2014 - Sep 2016
    Chandler
    • Headed the IP Verification of UART-Smartcard and AFE-Current Bias modules at unit level.• Created the verification requirements in the Freeplan tool based on the specification in the DOS.• Teamed with Architects and Designers to create the testplans. • Developed the unit level testcases for the above modules.• Filed bug reports (Jiras) and verified RTL fixes.• Developed scoreboard, monitors, sequencers and scenarios in VMM-based verification methodology to setup the testbench environment using System Verilog.• Constantly updated the environment components to support verification of new features being added in the design.• Performed the functional coverage analysis for modules by defining SystemVerilog assertions and covergroups.• Developed test-cases for integrating the (MCCP) modules at full-chip level.
  • Microsemi
    Engineer
    Microsemi Jul 2013 - Mar 2014
    San Francisco Bay Area
    • Developed Perl Script for generating macros library using verilog files.• Developed TCL scripts to automate the EDA tool to compile and PNR the SOC designs.
  • College Of Business, Sjsu
    Student Assistant
    College Of Business, Sjsu Feb 2012 - May 2013
    San Francisco Bay Area
    • Maintain administrative office tasks such as filing, running errands, data entry and computing.• Compiling Student grades into MS Excel spreed sheets for reporting purpose and deriving class statistics from the data.• Providing Audio/video support for lectures and class related events.
  • San Jose State University
    Graduate Student
    San Jose State University Aug 2011 - May 2013
    San Francisco Bay Area
    Completed the Masters Program in Electrical Engineering at San Jose State University.
  • Luxim Corporation
    Engineering Intern
    Luxim Corporation Jul 2012 - Nov 2012
    Sunnyvale California
    Primarily develop software and test PCB’s for a custom mixed-signal ASIC. Develop modules for communication with the microprocessor over UART, SPI, I2C, and DALI.Develop a state machine controller for an RF powered plasma lamp based on the RTX RTOS for ARM Cortex-M0 microcontroller. Day-to-day responsibilities such as software design, coding, and documentation, as well as PCB schematic generation.

Parth Zaveri Education Details

  • San Jose State University
    Electrical Engineering
  • D. J. Sanghvi College Of Engineering
    D. J. Sanghvi College Of Engineering
    Electronics
  • Vivekananda Education Society Of Polytechnic
    Vivekananda Education Society Of Polytechnic
    Indusrial Electronics
  • St Francis D'Assisi High School
    St Francis D'Assisi High School
    Secondary School Certificate

Frequently Asked Questions about Parth Zaveri

What company does Parth Zaveri work for?

Parth Zaveri works for Qualcomm

What is Parth Zaveri's role at the current company?

Parth Zaveri's current role is Senior Staff Engineer.

What schools did Parth Zaveri attend?

Parth Zaveri attended San Jose State University, D. J. Sanghvi College Of Engineering, Vivekananda Education Society Of Polytechnic, St Francis D'assisi High School.

Who are Parth Zaveri's colleagues?

Parth Zaveri's colleagues are Rajeev Sharma, Kai-Chun (Joy) Huang, Jaswanth Thota, Benjamin Chen, Rick Dong, Akhilesh Richhariya, Josh Baker.

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