As a RTL Design Engineer, I have been working on FPGA micro level architecture design and FPGA design flow for the past year. I have gained experience and knowledge of Xilinx development platforms such as Vivado 2020.1 and 2020.2, and I have used Verilog HDL and VHDL for RTL design and synthesis.I have also worked on various interfaces and protocols, such as AXI - Stream, Lite and MM, I2C, UART, and SPI, and I have contributed to the development of digital logic design for various projects. I am passionate about FPGA design, and I am motivated to learn new skills and technologies in this domain.