Parth Parekh Email and Phone Number

• Winter 2020:- VLSI Circuits and Systems for Data Communications (ELE 863)- Radio Frequency Circuits and Systems (ELE 804)• Fall 2019:- Digital Systems (COE 328 / EES 508)

• Conducted research on all digital delta-sigma TDC using the principles of time-mode signal processing• Designed all digital delta-sigma TDC from gate level to tape out ready layout.• Performed schematic simulation, symbol testing, DRC/LVS/PEX checks, floorplanning, placement, routing, power planning and post-layout simulation for different analog and digital circuits using Cadence virtuoso • Developed Verilog code with testbench to create different RTL design models and libraries for testing and debugging design issues related to timing• Designed and Implemented PVT compensation circuits such as slew-rate control, bandgap generation circuits• Performed time and frequency domain analysis, noise analysis and power analysis• Prepared detailed data sheets and technical reports

• Demonstrated and explained to students the use of TSMC 180 nm Cadence design system for layout implementation, simulation, and physical verification• Assisted students to understand, perform and solve the given labs/ tutorials/ project work• Supervised and facilitated labs/tutorials