Parth Rajan Email & Phone Number

Hyderabad, Telangana, India

Consumer Connectivity & Video

Dublin, County Dublin, Ireland

Leading a team of layout engineers to manage multiple projects for on time delivery. Setting up goals, objectives and deliverables for projects

Dublin, County Dublin, Ireland

• Working in the Dublin Design centre team to check feasibility of projects from various Business Units and seeing them through to tapeout if passing feasibility
• Carrying out feasibility check which included evaluating parent (donor) chip with new process, pdk version, new die area, new assembly type, new pad type and new wire bonding or new bump placement
• Working with switching DC-DC Integrated Power, layout of high current switching power FETs and associated circuit in application like Buck or Boost converters
• Taped out quad SPST and SPDT switches chip and Automotive USB chip as lead
• Training and mentoring new layout graduates

County Dublin, Ireland

• Working in the SerDes Team developing SerDes products up to 112Gbps on the latest CMOS Finfet nodes. Layout of circuits for the high-speed transmission and recovery of data over wired links, including equalisers, PLLs.
• Helped design and test pcell wrappers over TSMC standard cells in 7nm process for ease of use for layout
• Creating and Presenting PowerPoint slides about research on power grids used in 16 and 7nm nodes
• Trained and certified on 16nm & 7nm Finfet processes

County Cork, Ireland

1. Worked on Analog and Mixed Signal blocks, verifying, taping out & archiving data2. Experience in Top level layout, managing a team as lead layout, creating schedules for projects and keeping track of schedules by organizing weekly meetings3. Experience of working on 2 ADC projects from scratch which included layout work on fuses, references, LDO’s.

County Limerick, Ireland

1. Finding cadbugs in processes and helping CAD engineers to fix them2. Conducting top level reviews and creating verification documents3. Used Digital routing tools for non-timing driven digital design4. Created Padrings, included creating analog & digital ESD pads from scratch5. Familiar with CMOS, BiCMOS and BCD processes - 0.18um, 0.13um, 55nm

County Limerick, Ireland

1. Coordinated with design engineers to understand the specific requirements of matching, shielding, current density for full custom IC layouts2. Layout tools used: Cadence Virtuoso Layout Editor(cadence version IC5 & IC6) and Cadence Virtuoso XL(cadence version IC6)3. Verification tools used for LVS, DRC, ESDDRC, ANTENNA: Hercules, Calibre & Dracula4..

County Limerick, Ireland

Generating layouts for devices on wafer, Probing wafers after manufacturing, Comparing results of probingTasks in Manufacturing Fab – splitting, searching and transferring wafers

B.Eng. (Hons), Electronic Engineering, 1:1

Senior School Certificate Examination, 1:1

Secondary School Examination, 1:1