currently working for intel.

• Experienced to Predict complexity/delay/Parasitic/Coupling/EM/IR-Drop and etc. • Hands on experience in CMOS matching layout techniques for precision Analog circuits. Familiar with Memory Layout design architecture. • Hands on experience with advanced technology nodes like 130nm, 40nm, 10nm, 7nm, 5nm. Aware of DFM rules, Antenna Effects, Latchup, EM and ESD.• Solid understanding of CMOS process technology and associated issues in deep sub-micron technology like Optical Proximity Correction, LOD, Proximity Effect and Shallow Trench Isolation.• Good in High-Speed Low-Power Multi-Vt Standard Cell (Layout) Library Development and Qualification Can do least parasitic layout in low area and also expert in Multiple pattern layout design for sub-nm technology. hands on experience in Intel 10nm, flows toplevel integration. Handling part of team 4 people.