Parvathy . Email & Phone Number

Thiruvalla, Kl, In

Kochi, Kerala, India

Digital Design Engineer➢ Developing strategies for the design of the digital part of a Radio Frequency (RF) Transceiver System on Chip (SoC) with integrated RISC V core for Sub-GHz applications in collaboration with IIT Kanpur and Ministry of Electronics and Information Technology under the Chips to Startup (C2S) program.➢ Coordinating the RTL Design team in the designing and integration of the digital blocks from architectural level.➢ Executing strategies for verification plans of the integrated Radio Controller part of the Sub-GHz RF Transceiver comprising of Serial Peripheral Interface (SPI) peripheral with Communication Controller, FIFO, Packet Controller, Framing / De-framing Module, Encoder / Decoder Module.➢ Tackled several multi clock domain and timing issues during different stages of design and functional simulation. Addressed warnings and errors from tools at various stages of design development for RTL sanity.➢ Collaborated with team to establish efficient unit-level functional verification methodologies, including FPGA testing.

India

Working in collaboration with Silizium Circuits Pvt Ltd under the Chips to Startup (C2S) program by the Ministry of Electronics and Information Technology (MeitY).

Kochi, Kerala, India

RTL Design Engineer ➢ Pioneered in the field of RTL Design. Attained familiarity in RTL design and front-end design tools and flows.➢ Developed sound knowledge in Digital System Design. Trained in UNIX, Verilog, and System Verilog.➢ Consolidated knowledge about clock domain and reset domain crossing, synchronizers, isolation and level shifter cells and power management techniques. Familiarized with static timing analysis (STA) concepts and waveform analysis.➢ Developed a basic level understanding towards various signoff tools for RTL including Lint, CDC, DFT (SpyGlass tools), VCLP, ATPG, and Caliber. Conceptualized with running Synopsys VCS and Verdi using Xming in PuTTY.➢ Demonstrated good ability to participate well in a team. Illustrated excellent communication and leadership skills, initiative-taking and well-organised.

➢ Coordinated the 2022 batch placement drives and managed to accomplish the highest result of 91.3% placement of the B.Tech batch and a total of 60% result from the whole department including MTech and MSc batches.

➢ Modeled popular electrical and physical systems to tune the controller for a perfect response using Scilab Xcos. ➢ Developed a project on designing a model for the flight of a drone and assessing the pitch, yaw, and stability response of the body to an input.

Bachelor Of Technology - Btech, Instrumentation Technology, Cgpa - 9.34 (University Topper)

Activities and Societies: - ➢ Student Placement Coordinator ➢ IRES/SEDS CUSAT Member ➢ HR Head - SpaceUp CUSAT 2022 ➢ Compered.

Aissce - 83.6% ; Aisse - Cgpa - 10 (School Topper - Aissce & Aisse)

Activities and Societies: - ➢ Deputy Head Girl (2017-18) ➢ Attended an international conference on cybersecurity called cOcOn X in 2016.