Software Engineer
CurrentCurrently a part of a team designing a novel RISC-V CPU architecture, working on a cycle accurate Micro-architectural System Simulator written in C/C++.Developed a C++ library which decodes ethernet data frames carrying stock market data encoded according to proprietary protocols, to verify FPGA kernels used in High-Frequency Trading applications.Implemented a TVM based ML inference pipeline including a bench-marking tool targeting a RISCV64GC core using Python (https://github.com/accelr-net/tvm-riscv-demo).