Currently a part of a team designing a novel RISC-V CPU architecture, working on a cycle accurate Micro-architectural System Simulator written in C/C++.Developed a C++ library which decodes ethernet data frames carrying stock market data encoded according to proprietary protocols, to verify FPGA kernels used in High-Frequency Trading applications.Implemented a TVM based ML inference pipeline including a bench-marking tool targeting a RISCV64GC core using Python (https://github.com/accelr-net/tvm-riscv-demo).

Worked with a team of FPGA developers tasked with building an Apache Solr/Lucene hardware accelerator for a stealth mode US startup.Developed and maintained a C++ and Python CocoTB based verification framework used in the project.Developed Verilog RTL modules based on C++ hardware reference model built by senior engineers and Involved in testing, debugging and fixing the C++ reference model and RTL design throughout the period.Involved in developing several Python scripts to dump and analyze intermediate data generated by Apache Solr.Developed a test tool to perform bench-marking tests to compare vanilla Solr and the FPGA accelerated Solr versions.

Worked with a team from USA, India and Sri Lanka, building a Hardware Accelerated Computing solution for an open source search platform.Developed a hardware model for a hash function using C/C++ and integrated with the existing Java codebase using JNI. Wrote an OpenCL kernel for the function using Xilinx Vitis SDK. Wrote Python scripts to automate extracting textual data from CSV and PDF files, reformatting and writing to JSON files.

Contributed to research and development of the core architecture of an upcoming product.Developed various proof-of-concepts using C/C++, JavaScript & WebAssembly with OpenGL.