Pascal Meier Email & Phone Number

Design engineer in Automotive BU- Digital designer, SERDES links for ADAS and infotainment applications- Functional safety for automotive design.- Functional verification for SERDES, RF.

San Francisco Bay Area

Digital and mixed-signal verification for RF products.

Own the design of scan and memory BIST components for microprocessors. Integration of scan controllers and across the chip. Work with block owners to resolve physical/timing issues associated with scan. Work with Product Design Engineers to identify issues in RTL design leading to low test coverage. RTL simulation & verification of operating modes for scan.

Intel Corporation

Design of high-speed serial I/O PHY components for QPI/PCIe. LC-PLL design & characterization for high speed signaling. Board level signal integrity analysis, research into flex cabling for high-speed channels. 5 patents awarded.Mixed-signal verification of SERDES components: I/RCOMP training logic, PI training, full link PHY bringup.Led the physical.

Intel Corporation

Floorplanning for microprocessor designs. Analyzed routing congestion, prepared reports for physical implementation for multiple blocks. Supported custom clock routing tools. Assessed new physical design tool capabilities.

Doctor Of Philosophy (Phd), Computer Engineering

Bachelor Of Science (Bs), Computer Engineering