Patrick Donaldson Email & Phone Number

Deer Park, Ny, Us

Upton, Ny, Us

Designed a test system using a Xilinx Artix-7 FPGA to test a critical Digital card in the Quench Detection subsystem of the RHIC Collider.

Digital System Architect (FPGA)Consultant: Digital Signal Processing, Video Signal Processing, Motor Control, High-Speed Interfaces. Corp-to-Corp contracts OnlyLatest Contracts:- 2020 - Present Brookhaven National Laboratory - 2018-2019: Ensco (Blackhawk Helicopter Video Processor for Mission Management Computer) - 2019-2020: Flir Systems (Video Processing and motor Control FW design)

Wilsonville, Or, Us

Coded modules for multiple applications, video, motor control, multiple protocol serial communication. Managed updates of HDL library components in VHDL and System Verilog including test benches for each library update or new module entry.

Vienna, Virginia, Us

Consultant, for Ensco's DO254 effort to guide Lockheed Martin with DO254 Design plan for the next generation of Black Hawk air defense vehicle. Included design requirements capture and planning documents for the MMU (Mission Management Controller) an embedded FPGA video processing unit with multiple protocols.

Design of Controller/Arbiter/Scheduler on an ARM Embedded Xilinx 7-series FPGA for a Fiber Optic Gyroscopic Accelerometer/Inertial Measurement Unit w 1000Base-KX ethernet with IEEE-1588 PTP time synchronization protocol.

Cleveland, Oh, Us

DO-254Part of team to develop, the primary flight controller Inceptor Interface Module for Bombardier's C-Series BD-500 jets. Responsible for ΔΣ A to D interface in accordance with DO-254 guidelines. Captured Design requirements from System and Safety Requirements an existing DO254 Planning Documents.Tools: Doors, Mantis, Excel

Newport News, Va, Us

DO-254Managed DO254 project for ICG’s NxtLink ICS-220A Iridium communications system digital interface (VHDL on a Xilinx CPLD) Designed in accordance with DO-254 guidelines. (DAL D). VHDL needed to be redesigned for DO254 compliance and a formal verification testbench was created in VHDL. Wrote the PHAC and outlined all the documents called out in the PHAC.Tools: Doors, Mantis

Cleveland, Oh, Us

Part of team to design the fuel pump control system, A350 Airbus. Analog, Digital, FPGA, Motor Control. Everything from parts derating for system MTBF analysis to design of a test fixture for motor ramp-up test and debug. Mil-Std for reliability (MIL-HDBK-217) RTCA DO-254 DAL-BTools: Doors, Mantis, PSPICE CADENCE

Bethesda, Md, Us

Part of team to design of a real time FLIR (Forward Looking Infra-Red) video image de-rotation system for the Zumwalt class of Navy Destroyers. on a single Virtex-4 FX100 FPGA Responsible for designing and VHDL coding of the Control Logic / Frame Boundary Generator (CL/FBG) module. Serial video data cane in through the Rocket-IO SerDes with frames of video data redundantly stored in QDR2 RAM. Pixel data could be read out RAM in bursts to capture an N x N tile fed to an interpolator /averaging module and onto the processing module that was a WW realization of a DSP algorithm. The CL/FBG received angular data from a LUT that held sine/Cosine data converted from an angular sensor. The CL/FBG would generate the destination pixel address and frame boundary from the source pixel address, source frame boundary and the angular data from the LUT and the timing data to the Interpolator/Processor.1Gb Rocket IO GTX SERDES, QDRII SRAM, MATLAB, Xilinx ISE, DSP48 MODELSIM

Wilmington, De, Us

Consultant.Part of a large ASIC Development team for a 2G/3G GSM/CDMA baseband system.System was first modelled using a modem board with two processor daughter cards designed in house. The Modem board interfaced to a Radio interface board with Infineon (Thor) cell phone radio modules.This modem board contained 2 Startix-II FPGA's for CHIP and Symbol processing. The layer -1 proc card used a Startix-II FPGA with a softcore embedded ARM9 while the layer 2/3 processor card used a hardcore embedded ARM9 on an Altera Excaliber FPGA.The modem board and layer-1 processor boards were combined into a single ASIC. In my second year as a consultant there my team designed the verification platform for this ASIC. The second processor board was replaced with a GSM ASIC from Infineon.

Us

DO-254Managed the Distributed Built in Test (BIT) for Mission Management Processor on Boeing’s x45 JUCAS Aircraft for dual-G4 SBC, VME64 system. Actel Prosaic FPGA on discrete I/O card verified to 98% coverage upon completion of BIT. Project was compliant under Mil-Std for reliability (MIL-HDBK-217) (HBK-HW-55) and BIT Design Process (HBK-SYS-9). RTCA DO-254 DAL-ATools: Doors, Mantis

Wolverhampton, Gb

Designed the FPGA Brushless DC Motor Controller for LRLAP projectile in Lockheed Martin's AGS System for the Navy Zumwalt class of Destroyers- Designed and implemented the control logic and controller’s transfer function using Finite state machines and RTL in VHDL. Actel ProAsic FPGA MATLAB used for generating controller transfer function. Sub designs included UART, pos trackers, ARINC, MIL-STD-1553, DAQ, digital filtering and PWM generators. Project conformed to RTCA/DO-254 guidelines. DAL-BActel’s Libero tools, Synplify, ModelSim and MATLAB, VHDL

Us

Designed the PCB for the front end of a Calibration Test Set SONAR system. A mixed signal system on a 6-Layer PCB which generated arbitrary waveforms selected by the user. The user would upload a data file for a waveform to the local memory on the Altera FPGA. The system was also able to detect waveforms generated by the SONAR and return a value in linear or dB format to the front panel. All digital circuitry was designed targeting an Altera FPGA in Quartus including local memory and configurable digital filters. The analog circuitry included A2D, D2A and modulated waveform detection circuitry.Altera Quartus-II, MODELSIM, MicroCap-7, PSPICE, OrCAD, MATLAB, VHDL

Armonk, New York, Ny, Us

Was part of the development team for the E-Beam lithography, Beam controller ASIC. I Designed the e-beam deflection and control modules for the system which were modeled in an Altera Flex 10K FPGA using Quartus-II tools. The FPGA was on a 6U card in a VME64 chassis. A Cypress CPLD was used to interface to the backplane due to the deterministic timing of CPLDs The VHDL Code was simulated in ModelSim and then debugged in-system.

Wilmington, Ma, Us

Joined this startup company when it was White Mountain DSP. Acquired by ADI in 1999 as ADI DSP Tools Division.Designed DSP app boards for various TI DSP families. Board level design of some simple boards holding a single DSP, some peripherals like SRAM, A to D, D to A, P/S mixed signal circuitry etc. Interfaces were JTAG, PCMCIA, ISA boards used as DSP emulator tools, starter kits and development boards. C projects developed in Code composer since it’s in-line dissembler was ideal for debugging the huge instruction sets of the DSPs.This position was my introduction to Xilinx FPGAs. Board designs were originally captured using OrCAD in win 3.1. When company upgraded to Win NT schematic capture was done in ViewDraw from Viewlogic’s Workview Office. White Mountain was sold to ADI and I departed to become an independent consultant.VHDL, C, Code Composer, OrCAD, Viewlogic Workview Office (ViewDraw, ViewSim, View Spice, SpeedWave VHDL simulator)

Initially responsible for component derating and procurement of commercial off the shelf (COTS) equipment when possible. Worked on Army Platform Automatic Test Systems (APATS) which was a VXI chassis with mostly COTS instrumentation cards. The VXI chassis was interfaced via GPIB/HPIB to a computer which ran Labview Virtual Instruments (VI). Attended a 1-week, 40-hr training session for Labview Certification.Tested existing and in development RF components and systems using Teledyne Labtech and HP vector and scalar network analyzers. (HP-8510) for the Navy’s MILSTAR test system.redesign a MILSTAR PCB cited for obsolescence due to the use of one-shot devices as digital timing components. PCB was redesigned as a proper synchronous digital version of the obsolete board implementing an AMD Mach-series CPLD in VHDL Using Labtech PCB tools.Worked on integrating an upgraded mixed signal MILSAR LRU that implemented a Motorola 56000 DSP. Was trained on In Circuit Emulation (ICE) of the DSP to debug HW and SW problems. Attended many courses offered by Raytheon e.g., VHDL, C++ and “Kalman Filters as your friends” taught by Raytheon’s own Dr. Eli Bruckner. Teledyne Labtech, HP RF instrumentation, ARINC, Mil-STD-1553, Arinc429, VHDL, AMD MACH-series CPLDs, VXI/VME rack mount test equipment such as oscilloscopes and logic analyzers.

worked with people who were struggling to satisfy their math requirement(s).

Testing and customizing microwave mixers, couplers and amplifiers from 2 to 40 GHz using vector and scalar network analyzers to measure S-Parameters.

Amityville, Ny, Us

ET Stuff

Washington, Dc, Us

Test, repair and maintain communication and radar equipment.