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Am currently an Engineering Manager at Supermicro, specializing in architecting AI/ML solutions, MLOps, and deep learning. With a background in system/platform R&D and FA/QA, I manage a team specializing in AI with a point of convergence on Intel's AI Accelerator product lines (Gaudi, Xeon 6, Flex DCGPU).We collaborate across technical teams and design impactful solutions highlighting Intel's software and hardware stack's influence on Deep Learning and GenAI workloads through . We also bring expertise in production deployments of AI tools to a broad audience of student, commercial, and enterprise customers.My mission is to help clients meet and exceed their system and datacenter needs and ensure their solution is as efficient as possible using Supermicro's hardware and software products.
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Senior EngineerSupermicroSan Jose, Ca, Us -
Engineering ManagerSupermicro Sep 2023 - PresentSan Jose, Ca, UsOversee the end-to-end product development lifecycle of Intel's AI accelerators - Gaudi 3, Gaudi 2 and Intel Max (1100, 1550) - within Supermicro.Overall, I implement robust CI/CD pipelines and ensure seamless integration of new features and products. Work closely with cross-functional teams to deliver high-quality, scalable, and reliable solutions that meet customer needs and business objectives. -
Senior EngineerSupermicro Mar 2021 - Sep 2023San Jose, Ca, UsOversee the end-to-end product development lifecycle of Intel's Datacenter Flex GPU and Gaudi 1 product lines within Supermicro.Oversaw the design, development, and integration of new Intel-based products and features and ensured these products were developed in line with business goals, user needs, and technical feasibility.Drove the adoption of best practices in software development, including code reviews, testing, and documentation.Planned, prioritized, and managed multiple projects and tasks, ensuring timely delivery and alignment with strategic objectives. -
Senior Staff EngineerSgs Consulting Sep 2020 - Mar 2021Princeton, New Jersey, Us -
Test EngineerProtingent Apr 2019 - Sep 2020Bellevue, Wa, UsTest Execution Engineer, Microsoft Certification ProgramTechnology Enabling & Development - R&DRepresented Samsung Semiconductor regarding their Microsoft Windows Certification and Azure SIP test programs for Tier 1 and Tier 2 NVMe and SAS enterprise and datacenter vendors. • Collaborate with Tier 1 customers on evaluation, performance testing and integration of products.• Responsible for all hands-on support and debug on all Pre-Qualification (PQ) and sanity testing through customer FW release candidates.• Responsible for all Hardware Lab Kit (HLK), Storage Spaces Direct (S2D), Private Cloud Simulator (PCS), and Azure System Interoperability Program (SIP) test configuration creation and operation of all testing in order to obtain Microsoft certification.• Responsible for planning, executing and managing Tier 1 customer AQL Development and Qualification and SIP Testing processes. -
Sr. Applications EngineerTriple Crown Mar 2016 - Jul 2018Austin, Tx, UsResponsible for and established statistical confidence by identifying sample size and acceptable error and determined levels of confidence. Represented Advantest America for Micron regarding AAI’s MPT3000 product line. Provided leadership to others in various Micron departments and acted as Advantest’s prime contact on high level projects while training and mentoring less experienced employees.Provided production support, often on short notice, on a wide range of topics from board level problems, software configuration, production test procedures (Python, C++), test and training.Provided input on quality to Production Development teams and recommended producibility improvements by facilitating process reviews. Addressed technical data packages, manufacturing methods, equipment tooling and training.Worked and interfaced daily with Micron’s Product Qualification and Product Validation teams in regard to test development with Python and C++. Was integral in introducing a Python to VAST API scripting solution where Micron was able to bypass using Advantest’s GUI software automated testing solution (Selenium-based) and call Advantest’s proprietary APIs in a scripting form.Used Continuous Improvement methodologies to assess quality and perform evaluation of defects, and provide engineering level technical expertise regarding recurring problems reported by customers. Assessed and determined the cost of and responsibility for products or materials that did not meet required standards and specifications by performing difficult statistical analysis. Identified quality performance, trends and corrective action by coordinating with customers and suppliers. -
Field Applications EngineerSilicon Motion Aug 2015 - Jan 2016Jhubei City, Hsinchu County, TwResponsible for Prototype Embedded board bring up and testing of Intel’s embedded storage and SSD controller solutions, remote development setups, engineering inventory maintenance. Represented Silicon Motion for Intel Corporation by interfacing with customers and regulatory agencies regarding division process.Responsible for technical support, detailed problem determination, and problem resolution of issues. Interfaced between production, Hardware, Software and Quality teams to resolve product related issues as required. -
Lead Debug EngineerIntel Corporation Oct 2014 - Aug 2015Santa Clara, California, UsDrove development and testing of Intel's SSD DC P3608 (HH/HL) series and helped bring about Intel’s SSD 750 drives which was a 2.5" 15mm drive using PCIe NVMe 3.0 x4 lane technology using Intel’s 20nm MLC NAND flash memory.Prepared comprehensive reports by collecting, interpreting, analyzing, and summarizing data and make recommendations. Analyzed proposed changes in methods and materials.Refined and enhanced Intel SSD products and processes by applying Continuous Improvement and key lean manufacturing/production principles and techniques to critical areas of testing and validation.Worked closely with other departments (mechanical, software, production, etc.) to support ongoing design tasks and projects; coordinates efforts as needed to achieve project deadlines. Collaborated with documentation team to provide technical information and participate during review cycles. -
Engineer Level 2Hgst, A Western Digital Company Sep 2011 - Oct 2014San Jose, Ca, UsDrove the design, planning and implementation of the following server and storage consolidation solutions: VMWare ESX 4.1, VMWare ESXi 5.0/5.1/5.5, RHEL 6.0 / 6.1 / 6.2, SLES 11 SP1/SP2, DELL PowerEdge T610/850/R710/R720, IBM X3650 M3 and x3850, Super Micro X8DTH-if, Super Micro X9DR3-F. Also set up NFS/CIFS clients on all platforms and developed key documentations and templates which were used by various departments to maintain and troubleshoot their environment. This also included automating operating system installations.Performed process reviews and monitored and evaluated internal and supplier Quality Control functions and benchmark facilities in order to assure assemblies parts and material met or exceeded requirements.Worked to characterize, debug malfunctions and data errors, isolate root causes, and develop solutions by resolving firmware and system bugs during various NVMe & PCIe bus states and transitions by performing product validation tests per specified test plans.Performed quality functions onsite and was involved with supplier selection and development activities related to New Product Introduction (NPI), prototype and production business. -
Storage Validation EngineerIntel Corporation Aug 2007 - Apr 2011Santa Clara, California, UsCCG/CSE RST/RSTe Integration & Performance BenchmarkingResponsible for verification and validation testing for Intel’s SSD controller PC29AS21BA0 on 10-channel 32nm architecture. Coordinated various performance tests. Monitored, assessed and improved performance and reliability of bench systems and components.Developed tests and test bench components from high level verification plans and debugged failing tests. Supported Operations and Engineering activities such as debug, raw class, and stress checkout from burn-in support to temperature-related experiments. -
Media Validation EngineerIntel Corporation Mar 2009 - Mar 2010Santa Clara, California, UsDHG-CPE-CE Software Engineering LabManaged the integrating, testing, installing, and configuring factory automation software systems and satellite encoders and receivers. Followed the automation change control process with respect to testing and documentation while making a fully supportable application. Responsible for some software development of related enhancements, supplemental systems, and supporting monitoring tools.Responsible for silicon and system validation, developing, running and debugging software and firmware in hardware boards, FPGAs, and emulators during both the Pre and Post silicon phase of development. This included ownership of SoC silicon module debug.Communicated with multiple Geo silicon design engineers, architects, Driver and Firmware software developers and application engineers on customer support. This required creating, reviewing, and executing system validation test plans and communicating progress and results in a timely manner with input from multiple stakeholders. -
Lab And Execution TechnicianIntel Corporation Aug 2007 - Sep 2008Santa Clara, California, UsOversaw all upgrades for internally supported services or equipment. Performed diagnosis, troubleshooting, maintenance, and repairing of hardware and software-based issues.Responsible for understanding various client and server build technologies, system patching, system management and auditing via manual and automated use. Supported and managed backup and storage devices, network related customer problems and requests, or support of telecommunications related equipment.
Patrick Fallon Skills
Patrick Fallon Education Details
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Devry UniversityComputer And Information Sciences And Support Services
Frequently Asked Questions about Patrick Fallon
What company does Patrick Fallon work for?
Patrick Fallon works for Supermicro
What is Patrick Fallon's role at the current company?
Patrick Fallon's current role is Senior Engineer.
What is Patrick Fallon's email address?
Patrick Fallon's email address is pa****@****ail.com
What is Patrick Fallon's direct phone number?
Patrick Fallon's direct phone number is +171494*****
What schools did Patrick Fallon attend?
Patrick Fallon attended Devry University.
What are some of Patrick Fallon's interests?
Patrick Fallon has interest in Technology, Red Sox, Nano Technology.
What skills is Patrick Fallon known for?
Patrick Fallon has skills like Windows Server, Hardware, Debugging, Ssd, Linux, Win 2012 Server, Win 2008 R2 Server, Hardware Diagnostics, Pcie, Scsi, Soc, Test Automation.
Who are Patrick Fallon's colleagues?
Patrick Fallon's colleagues are Julian Chen, Alvin Liao, Akira Shimaya, Karim Fahim, Vivek Boss, Josh Hernandez, Amos Musyoka.
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