• Successfully developed and launched DDR3 IP product based on UltraScale Kintex for HAPS-80 platform targeted for Deep Trace Debug feature. Implemented DDR3 IP with the flexibility of six combinations of connector locations. HAPS-80 systems are expected to be the best selling company hardware for 2016.• Improved Protocompiler product quality by providing test case to development team to locate software anomalies responsible for crashes. • Designed validation and test IP for HapsTrak3 GPIO boards. Wrote Tcl test scripts for QSFP and Riser8 cards. Created test plan for GPIO, QSFP, and Riser8 cards. Tested and delivered more than 1000 HT3 GPIO boards, and QSFP and Riser8 cards in the lab. • Trained test engineer. Transferred knowledge to manufacture engineer. Prepared test station and created TCL-TOP scripts in Synplex environment for test automation.• Provided technical support to CAEs to respond to customer needs. Reported errors in the technical papers and provided feedback to both the documentation and marketing teams. • Created file list using QBAR for Project Elessar, synthesized Rumi-III using Synplify Pro, placed and routed using Vivado. Performed System validation, debug and troubleshooting, including hands-on debugging in the lab. Worked with hardware models and partial designs in rapid states of change. Used diagnostic equipment such as JTAG, logic analyzer, and scopes and software including Verilog, C, C++, PERL, and Verilog/VHDL. Debugged ARM processor and DDR and DSP design modules, and ran regression tests in lab environment.

• Built Altera Stratix IV-based memory controller validation platform. Synthesized using Synplify Premier. Placed and routed using Altera Quartus. Ran ASIC/FPGA simulation using MAKE and Tcl scripts, and debugged RTL in Verdi. • Built FPGA validation platform for MPS2 project based on the HAPS-54 board. Defined FPGA architecture, the interface between MPS2 ASIC chip, Virtex-5 FPGA, and the test board. Created FPGA Linux/UNIX simulation environment in VCS/ModelSim and built test benches in System Verilog. • Applied RTL and System C coding to create the test bench to run object-oriented SystemVerilog simulations for the HDTV System on an SOC chip. Worked with architecture and design team to develop simulation and verification environments to prove the accuracy and to measure performance of the algorithm and RTL. • Worked on video interface such as Vby1, HDMI TX/RX, Component/VGA Video, composite video, Audio ADC, Audio DAC and display port. Created test plan, executed and achieved coverage targets. Created test benches in SystemVerilog to run simulations. Applied System-C and coverage driven random verification environment Open Verification Methodology (OVM) platform for validation testing.

• Led an engineering team of three members. Coached junior engineers. • Prototyped ASIC chips Baldur and Luigi2 in Virtex-5, and conducted functionality test through UART, XDB and RealView. These chips won significant market share in SATA/SAS storage market.• Brought up and validated DDR2 memory controller and PCI Express slave in Virtex-5 on HAPS-34 development board using Synplify Pro, ISE, ChipScope, FPGA Editor, PlanAhead, Logic Analyzer, Oscilloscope, and Protocol Analyzer. • Verified WiMedia Wireless USB System on Chip (SOC) using Synopsys Ultra Wide Band (UWB) IP in object oriented programming (OOP) Vera. Partitioned ASIC into two FPGAs. Conducted lab test for MOBA interface. Developped simulation environments used by test development team to exercise Matlab and Verilog models, as well as evaluate third party tools and develop methodologies which enhance ability to produce high quality ASICs.

• Led Project Real Time Watermark Embedder. Managed 6 people team. Brought up 300% increase in revenue. • Designed and simulated Real Time Watermark Embedder in Virtex-4 on Xilinx Development Board ML403 using Xilinx Platform Studio (XPS), ModelSim and ISE in System Verilog. Defined product micro architectures. Lab tested VBI Closed Caption Detection and Insertion board with Virtex-II Pro. Performed HW/SW feature integration and functional verification.• Designed Physical Layer Router (PLR) in VHDL by using Quartus enabling PLR to meet high speed timing requirement for DSL systems.• Designed Tone Detector using Matlab, Simulink, DSPBuilder and Quartus. Applied newest approach for implementing DSP cores in FPGA.• Wrote programs in VHDL for T1, E1, DS3, SONET handheld test and measurement equipment. • Implemented Lockheed Martin Missiles & Space project “VXI SERIAL IO Board testing with programmable data formatting” using Xilinx Spartan Device.• Designed Intellectual Property in imaging, video and audio processing cores which can be reused by customers and decrease their design cycles. These IP cores include MPEG-2, MPEG-4 encoder/decoder for SD analog video standards (NTSC, PAL) and HDTV standards, VBI standards. Digital signal processing cores include digital filters design, audio encoder/decoder.