Patrick Tsui Email & Phone Number

Patrick Tsui is a Engineering Manager at Intel. He possess expertise in asic, physical design, formal verification, timing, silicon and 9 more skills. He is proficient in Chinese.

Listed skills include Asic, Physical Design, Formal Verification, Timing, and 10 others.

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  Engineering Manager

  Intel

  Sep 1997 - Present - Santa Clara Ca

  Led a team of 20 engineers across Santa Clara CA, Hudson MA, Costa Rica and used state of the art tools/equipments to debug Xeon Server CPU and address blocking issue in areas of , tester/system content bring up, robustness and yield debug, optimize power and performance between tester and system, and close DPM gap to meet power/performance/quality requirement. 1. Server CPU Pre Silicon Validation: validated DFT features in pre-si validation through simulation and emulation.2. Server CPU post silicon debug and product development engineering: used advanced DFT feature and interface debug lab with advanced equipment to probe circuit to help defect isolation, identify speed path and close pre-silicon to post-silicon timing correlation. 3. CPU Physical design implementation: led a team to take RTL through ASIC implementation flow, including synthesis, clock tree implementation, P&R, formal verification and timing/physical closure for Intel chipset and CPU

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  Santa Clara University

  Msce/Mba