Hardware Design Engineer
Division of Finmeccanica, focusing on Analog, RF and Digital design solutions); Hired into Engineering Design Group specializing in the design of Department of Defense (DoD) recording products. Scope of duties encompassed system design as well as Analog & Digital , RF Design, PCB layout, VCO/PLL, Clock Distribution & FPGA Layout Design and Coding.1 GHz IF Digitizer Recording / Playback IO Board : Design, Layout and coding of FPGA based 500 MHz Ultra Wide Bandwidth, AD & DA both sampling at 1.333 Gsps, Input designed for 1GHz IF center frequency, IF chain includes gain and gain control.Multiple IF Digitizer Recorder & Playback IO Board: RF Design, PLL/VCO Design, and Coding of FPGA based IO boards with variable sample rate and IF inputs. IF front end includes switchable gain and gain control, and filter banks giving the capability to receive and transmit alternate IF frequencies. DSP processing using FPGA resources allowing for digital tuning, filtering, decimation and interpolation.
