Engineer Ii (Principal)
CurrentASRC Federal, Egg Harbor Township, NJ 5-2017 to PresentEngineer II, Principal • Hardware Engineer under the AJW 1462 group, second level engineering• ASR-9 Radar Data Communications Equipment Modernization project Designed a microprocessor-based communications circuit card assembly to interface with the radar receiver message interface processor (MIP) on the ASR-9 radar receiver backplane (the design implements Ethernet ports as part of a network communications system which provides air traffic TRACONs and control towers radar target and weather data which is currently accomplished by obsolete modems) Designed a microprocessor-based communications CCA to interface with the radar six-level and WSP weather processors and system control Wrote VHDL code for the FPGAs (Field Programmable Gate Array) which receive and format raw radar and weather data messages from the backplane to present to the processor on a local bus Designed an FPGA-based test fixture and wrote VHDL code to simulate radar and weather message data to test the circuit card assemblies in production Drew schematics and laid out circuit cards, which included layout of DDR-2 SDRAM, using Altium Designer CAD software• ASR-9 Modulator Pulse Assembly Control & Monitor Circuit Card Replacement project lead Performed circuit analysis of the PFN (Pulse Forming Network) slow and fast servo loop circuits Designed soft start circuit for the PFN Designed circuit to increase the adjustment range of the PFN voltage Researched alternate electronic components to replace obsolete components and incorporated into the updated design Replaced the obsolete FPGA and ported existing VHDL code to the new FPGA Drew schematics and laid out circuit card using Altium Designer CAD software Designed electrical test fixture for use in manufacturing test Wrote manufacturing test procedure Updated ASR-9 technical instruction books