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As a System Engineering at Meta, I lead a characterization team that optimizes inference and training for silicon solutions. With a BS in Electrical Engineering and multiple courses in AI and data mining, I have a strong background in developing and validating hardware systems for complex and innovative projects. Previously, I worked at X, the moonshot factory, where I developed 100% of the LTE subsystem test plans and created a ML pipeline to improve manufacturing yield from 60% to over 90%. I also developed a genetic algorithm to enable FCC certification and owned system level root cause and failure analysis. At Plume Design, I was instrumental in securing series B funding of 37 million dollars and increasing production yield by 22% on a high volume WiFi consumer product. I received a patent for power/thermal profiling and mediation and developed performance analysis tools with Pandas. I have over 6 years of experience in hardware engineering and characterization, and I am passionate about solving challenging problems with cutting-edge technologies.
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System EngineeringMeta Jul 2021 - PresentMenlo Park, Ca, UsLeading a characterization team focused on inference and training optimization for silicon solutions -
R&D EngineeringX, The Moonshot Factory Nov 2017 - Jul 2021Mountain View, Ca, UsDeveloped 100% of LTE subsystem test plans for both design, manufacturing, and in flight self-test verificationOwned LTE RF bringup, validation, and transition to manufacturingCreated ML pipeline to pinpoint manufacturing deficits and improved overall yield from 60% to > 90%Developed a genetic algorithm to optimize LTE performance and enable FCC certificationOwned system level root cause and failure analysis -
Hardware EngineeringPlume Design, Inc Dec 2015 - Nov 2017Palo Alto, California, UsInstrumental in securing series B funding of 37 Million dollars. Increased production yield by 22% on a high volume WiFi consumer product.Resurrected hardware design enabling the sale of millions of units.Brought proof of concept to high volume manufacturing in less than 9 months.Received patent for power / thermal profiling and mediation.Root caused RF desense issues.Developed performance analysis tool with Pandas.Used EDA (Exploratory data analysis) to track design improvements in high volume manufacturing and the field.Developed test, verification, and production plans for 802.11 and bluetooth consumer product.Designed and automated characterization lab in Python. -
Principal Manager Of Technical StaffQualcomm Atheros (Nasdaq:Qcom) May 2011 - Dec 2015San Diego, Ca, UsManaging a RF and mixed signal characterization lab focusing on 802.11 a/b/g/n/ac, Bluetooth, GPS, NFC, and LTE -
System Engineering ManagerAtheros Communications (Nasdaq: Athr) May 2007 - May 2011San Jose, Ca, UsManaging Silicon bringup and RF characterization of all Atheros chip sets across multiple geographies -
Senior Systems EngineerAtheros Communications (Nasdaq: Athr) May 2001 - May 2007San Jose, Ca, UsWrote software and developed algorithms used in high volume production (Perl, Labview)Designed production ready 802.11 WIFI reference designs including access points, mini-pci cards, cardbus adapters, and digital media adapters for retail, SOHO and enterprise marketsCreated wireless audio/video media card for use with home media centers and set top boxesEngineered custom boards for testing 802.11 system level sensitivity, multi-path, and throughput performance using Stamp, FTDI, and Atmel microcontrollers Established and implemented RF system level lab including infrastructure to automate DVT on all Atheros designsPartnered with customers to create solutions to meet desired specifications. Hardware interfaces included: PCI, MPEG, I2C, UART, USB, IR, JTAG, Local bus and SDIO.Coordinated designs, schedules and software across interdisciplinary teams and dispersed geographical locales including India, China, and Taiwan.Trained Field Application Engineers in the use of hardware and system implementationAcquired FCC certification on wireless reference designsWorked with ODMs to produce cost effective products in a timely manner
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Test Design Engineer3Com May 1996 - May 2001Marlborough, Ma, UsProvided and deployed high volume manufacturing test solutions for telecommunications devices.Designed model for allowable worse case transmission line characteristics via Powerview, SPICE, and Matlab.Developed algorithms to generate arbitrary waveform models for Jitter testing
Patrick Hanley Skills
Patrick Hanley Education Details
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California Polytechnic State University-San Luis ObispoElectrical And Electronics Engineering -
Stanford University School Of EngineeringMining Massive Data Sets (Cs246)
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Stanford University School Of EngineeringArtificial Intelligence: Principles And Techniques (227)
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UdacityArtificial Intelligence For Robotics (Programming A Robotic Car)
Frequently Asked Questions about Patrick Hanley
What company does Patrick Hanley work for?
Patrick Hanley works for Meta
What is Patrick Hanley's role at the current company?
Patrick Hanley's current role is Meta / Facebook.
What is Patrick Hanley's email address?
Patrick Hanley's email address is ph****@****gle.com
What is Patrick Hanley's direct phone number?
Patrick Hanley's direct phone number is +140877*****
What schools did Patrick Hanley attend?
Patrick Hanley attended California Polytechnic State University-San Luis Obispo, Stanford University School Of Engineering, Stanford University School Of Engineering, Udacity.
What skills is Patrick Hanley known for?
Patrick Hanley has skills like Rf, Wifi, Semiconductors, Testing, Mixed Signal, Ic, Debugging, Ieee 802.11, Perl, Systems Engineering, Analog, Lte.
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