Paul Schilling Email and Phone Number

Process Engineer in Azure Quantum for manufacture of topological quantum devices

Process engineer with extensive experience in micro LED fabrication, ALD process development and optimization, lithography process development and wet cleaning/contamination control processesExperience in process development, DOE, and SPC with Veeco Phoenix ALD, Temescal evaporators, AMAT Raider, automated wet benches, EVG spin track and nanoimprint lithography, Suss aligner

Process engineer in development of next generation VR hardware components

• Process engineer for development of lithography, deep RIE etch processes, and PZT films used in MEMS scanning fiber actuator• Lead equipment engineer providing equipment repair and support in place of vendor service• Consultant for cleanroom and facilities design and equipment acquisition for new MEMS fabrication cleanroom facility

Led metrology, lithography, and plasma etch sections of clean room; providing mentoring, new process development and routine process monitoringBecame the go-to person among clean room users for training, process development, and equipment repair due to quick response to inquiries and a positive customer experienceCreated successful interferometric profilometry processes for failure analysis on bare die and packaged device for RFID devicesCollaborated with Microsoft Applied Sciences Group researcher on fabrication of phase gratings, development of a silicon epitaxy process, microlens HF etching and ellipsometry techniques for characterization of optical coatings

•As a founding member of Supercritical Systems, Inc., a cleaning technology startup company, lead development of novel chemical formulations and processes that lead to sale of company to Tokyo Electron•Supervised a research group targeting development of cleaning formulations and processes for removal of photoresist residues for a variety of semiconductor and MEMS devices using supercritical carbon dioxide•Pioneered a novel post etch cleaning chemistry for porous CVD dielectrics that resulted in lowest observed via chain resistance in testing at Intel•Initiated a research project to develop a material for a polymeric chamber seal including defining material specifications, manufacturing prototypes, and designing a testing infrastructure which resulted in a robust, particulate free chamber seal

•Designed and conducted multistep syntheses of a variety of novel monomers used in the synthesis of poly(aryl ether)s for use as spin-on dielectric coatings in semiconductor manufacturing•Developed a novel ion exchange purification process for spin-on polymer solutions that produced a product with sub-ppb concentrations of alkali metals to meet requirements for bulk shipments of product to Intel for evaluation•Provided technical support to Honeywell engineers with process transfer of bench scale monomer and polymer syntheses to multi-kilogram pilot plant production•Developed skills in GC-MS, HPLC, FTIR, Raman, SEM, AFM, EDS, XPS and microscopy and polymer analysis using SEC, DSC, DMA, TGA, and light scattering analysis