Paul Colestock

Paul Colestock Email and Phone Number

A better starting point for the DoD and the Semiconductor Industry. Design driven from Atoms, to Assembly and AI. @ Midwest Microelectronics Consortium (MMEC)
Paul Colestock's Location
Salinas, California, United States, United States
About Paul Colestock

How you start a design has a big impact on the level of performance achieved and how long it takes to get there. With expertise across three Specialty Foundries, four EDA companies and two semiconductor startups, I help the DoD, Foundries, and their Customers and Partners go Further Faster by providing a Better Technology Starting Point and the right tools, services and design IP to achieve the most competitive and differentiated products.

Paul Colestock's Current Company Details
Midwest Microelectronics Consortium (MMEC)

Midwest Microelectronics Consortium (Mmec)

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A better starting point for the DoD and the Semiconductor Industry. Design driven from Atoms, to Assembly and AI.
Paul Colestock Work Experience Details
  • Midwest Microelectronics Consortium (Mmec)
    Director Of Commercial Innovation
    Midwest Microelectronics Consortium (Mmec) Feb 2024 - Present
    Dayton, Ohio, Us
    Finding, funding and shepherding innovators, innovations and infrastructure driving commercial impact in the Lab to Fab and Mission to Market paradigm.
  • Starting Point Silicon
    Founder, Cto And Solutions Architect
    Starting Point Silicon Mar 2023 - Present
    Where you start a design has a big impact on the level of performance achieved and how long it takes to get there. I help Specialty Foundries, their Customers and Partners go Further Faster by providing a Better Technology Starting Point and Help Along the Way.
  • Silicon Catalyst
    Advisor And Advocate
    Silicon Catalyst Apr 2015 - Present
    Startup Advisor, Candidate Screening, Semiconductor Innovation Advisor
  • Synopsys Inc
    Darpa Business Development For Aerospace And Government Go To Market Team
    Synopsys Inc Jun 2023 - Feb 2024
    Sunnyvale, California, Us
    Business Development and Solutions Architect for Aerospace and Government GTM team focused on DoD research and all things AI.
  • North Carolina State University
    Industry And Academic Advisory Board Member For Electrical And Computer Engineering
    North Carolina State University Jan 2018 - May 2023
    Raleigh, North Carolina, Us
    Advise the dean of the college of engineering on industry directions related to the wireless and semiconductor technology industry.Work with both the undergraduate and graduate engineering programs to align the curriculum for the jobs of the future.Mentor underprivileged and at risk students and sponsor and participate in graduate research programs.
  • Globalfoundries
    Director Of Design & Technology Leadership, Cto Office Mobile & Wireless Bu
    Globalfoundries Oct 2018 - Mar 2023
    Malta, Ny, Us
    RF Power Amplifier linear efficiency is difficult to achieve at mmWave frequencies.With Billions of 5G/mmWave PAs estimated to ship long term,Improving Linear Power Efficient Technologies is CriticalJoin Me in Connecting the World without Destroying the Planet!
  • Globalfoundries Rf Business Unit & Technology Development
    Director Of Rf & Mmwave Design Driven Development
    Globalfoundries Rf Business Unit & Technology Development Jan 2018 - Oct 2018
    Development and demonstration of next generation energy efficient RF and mmWave power device technologies via exploration, implementation and optimization of mmWave and 5G circuits to connect the world without destroying the planet.• Build and manage highly effective IC design teams to connect mmWave product requirements to the underlying technologies to drive the development of next generation technologies.• Deliver technology capability, readiness and yield via implementation of a ‘By Design’ methodology in GlobalFoundries current and next generation RF and mmWave focused technologies including SiGe, RFSOI and FDSOI.Focus• High Performance and energy efficient connectivity: 802.11ac/x, 5G mmWave and auto radar modules, tiles and transceivers with integrated and standalone RF power front ends.
  • Globalfoundries
    Sr Dir Platform Design Solutions Engineering
    Globalfoundries Jul 2015 - Jan 2018
    Malta, Ny, Us
    Delivering a new kind of foundry experience via exploration, implementation and optimization of wireless circuit architectures and innovative technologies to improve customer and partner time to product.• Build and manage highly effective IC design teams to improve time to product for wireless connected systems and semiconductors• Deliver design innovation, differentiated design IP, technology capability, readiness and yield via implementation of a ‘By Design’ methodology in GlobalFoundries standard and differentiated semiconductor technologiesTeams and deliverables:• High Performance connectivity: 802.11ac, 4G and 5G mmWave, auto radar (modules, tiles, transceivers with integrated and standalone RF power front ends)• Wide, local and personal area low power connectivity: Dual Mode LTE CatM1/NB-IOT, 802.11bgn and 802.15.4., BT 4/5 (modules, basebands, transceivers with integrated RF Power front ends)• Full range (low power vs high performance) sensor interfaces: imager, 4G/5G, IOT data convertors and interfaces (wan/lan/pan)• Highly optimized SOC precision analog design IP including signal generation (DVCO, ADPLL ...), power management (charge pumps, LDO ...) and data interchange interfaces (SERDES ...)
  • Globalfoundries
    Sr Director Of Segment And Strategic Marketing
    Globalfoundries Jul 2011 - Jul 2015
    Malta, Ny, Us
    Create and lead a world class team of semiconductor product and design engineers to deliver the core market and product specs for differentiated semiconductor products covering leading edge, mainstream and market specific semiconductor solutions.Delivered: Mobile, Industrial, Consumer, Automotive, Compute and Connected segments with product focused segment plans and investment business cases including everything from analytics and requirements to customer acquisition strategies.
  • Agilent Technologies, Eesof Eda Division
    System To Silicon Wireless Design And Verification Solutions Architect And Evangelist
    Agilent Technologies, Eesof Eda Division Jun 2008 - Oct 2011
    Santa Clara, Ca, Us
    • Identify and drive design innovation opportunities, requirements and deliver solutions with R&D.• Implemented innovative reference design strategies including RF and mmWave design methodology guide across EDA (Cadence, Ansoft, Xpedion) and foundry partners (TSMC, Jazz Semi, IBM).• Manage internal deliverables and overall business success through customer focused segment strategies, differentiated wireless design and verification products, regional business development activities and outbound marketing events and associated eco-system collaborative activities.
  • Cadence Design Systems
    Director Of Wireless Design And Implementation Methodology
    Cadence Design Systems Feb 2006 - Jun 2008
    San Jose, California, Us
    Plan, design, implement and document a set of wireless reference designs and associated Best in Class design and implementation methodologies to transform the way Cadence communicates with customers.• Authored Wireless Vertical Segment Application Strategy and Segment Requirements.• Created top down Wireless Vertical Segment design requirements for digital, analog and RF.• Responsible for the Vertical Kit Plan (MRD), managing engineering deliverables across multiple teams, validating delivered solutions and driving business success.• Developed strategies for Sales and Technical Field Operations to incorporate a wireless focus into customer facing activities including workshops direct customer interaction.• Provided a lead technical role in Cadence Customers Customer Relationship supply chain program for wireless.Delivered:• Wireless SOC Low Power Implementation Design Methodology and Implementation Guide (65nm 802.11bgn digital baseband)• Wireless SOC Functional Verification Design Methodology Guide (65nm 802.11bgn digital baseband)• Wireless RF Design Methodology Guide (180nm/65nm 802.11bgn radio/transceiver)• Systems in Package Co-Design Methodology Guide (180nm transceiver, 65nm baseband, FE components)
  • Napali Technologies
    Corporate Director
    Napali Technologies 2008 - 2008
    Early stage startup designing and leveraging innovative RF transceiver and front end module concepts to bring next generation LTE to a broader market.
  • Jazz Semiconductor
    Director Of Wireless Technical Marketing, Design Ip And Applications Engineering
    Jazz Semiconductor Aug 2002 - Feb 2006
    Us
    • Early outside hire after Jazz spun out of Conexant in 2002.• Developed Customer Product Requirements Roadmap for silicon mm-wave and RF technologies.• Directed IP design effort for RF PA power cells and other associated components.• Created industry's first foundry reference design concept and product by designing and delivering complete WiFi based RF transceiver and associated design IP blocks and methodologies with internal and EDA/IP partners.• Conducted competitive Foundry analysis for SiGe, advanced RF CMOS, RF MEMS, silicon Nanophotonics and High-Voltage CMOS. • Co-managed device modeling team and created/managed world class RF pre/post sales applications team.• Drove internal efforts in product qualification, design kit and flow enablement, and technology development.• Led strategic tier 1 customer engagements for leading edge solutions development and deployment.
  • Hesson Labs
    Vp Product Engineering, Applications & Test
    Hesson Labs Mar 1999 - Aug 2002
    • Led product engineering on all Hesson Labs IC products (Network Processor, Switch Fabric, integrated 1-10 GB Ethernet, Fibre Channel, SONET OC12-OC192 serial interfaces).• Planned, developed, implemented and managed all post circuit design activities from netlist to engineering qualification/sampling including silicon engineering and qualification.• Developed high speed digital test and measurement environment for multi gigabit physical layer transceivers and performed all test, measurement and qualification activities including tape-out, silicon debug and reliability analysis.• EDA/CAD and Foundry Technology manager.• Developed hierarchical technology migration infrastructure and design rule correct automatic power and ground connectivity tool.
  • Silvaco International
    Director Of Austin Technology Center
    Silvaco International 1993 - 1999
    Santa Clara, Ca, Us
    • Built the Austin Technology Center focused on System to Silicon physical and electrical EDA for Next Generation Technology and Product Development.• Built and managed Central US territory from the ground up including sales, critical support, design/development engineering teams and 3rd party relationships.• Managed development and implementation of strategic next generation products including Virtual Wafer Fab TCAD, Utmost Spice Modelling and Test hardware/software, and RF/Wireless Harmonic Balance simulation engine.• Senior technical specialist for circuit simulation, implementation (EDA), multidimensional physical simulation/modeling.
  • Texas Instruments
    Mmwave Design Intern
    Texas Instruments May 1985 - Aug 1987
    Dallas, Tx, Us
    TI Defense Systems and Electronic Products Group (DSEG): mmWave Design Engineering Masters Fellowship• Term 1 DSEG: Characterization and design of Power Amps and RF switches for phase array radar.• Term 2 DSEG: RF PiN diode switch element technology bring up, production test development and characterization.• Term 3 Central Research Lab & funded Masters Thesis: Investigation of Defect limited storage time effects in vertical PiN diodes for microwave applications.
  • United States Navy
    Advanced Electronics (Et) Petty Officer
    United States Navy Oct 1977 - Oct 1983
    Washington, Dc, Us
    • Ships Intermediate Maintenance Facility, Mayport Florida - Troubleshooting and depot level repair of advanced electronic systems. - Managed high reliability repair lab and only ET certified to repair to original MILSPEC. - Sailor of the month, quarter and year 1993.• USS Mount Baker, AE4, various locations, special operations - Certified nuclear weapons security guard, radio/radar operation & maintenance/repair.• Nuclear powered submarine USS Sam Rayburn, SSBN 635 - Operate, maintain and repair high availability radar, electronic countermeasures and inertial navigation and supporting computer and location/positioning systems to enable positional accuracy for missile launch target of tens of feet over a minimum of 5000 miles.

Paul Colestock Skills

Semiconductors Ic Mixed Signal Eda Rf Semiconductor Industry Electronics Cmos Analog Asic Product Management Wireless Product Marketing Technical Marketing Simulations Circuit Design Soc Product Development Integrated Circuit Design Strategy Integrated Circuits Mems R&d Business Development Design For Manufacturing Silicon Radio Frequency Engineering Management Product Launch Application Specific Integrated Circuits Design Research

Paul Colestock Education Details

  • The University Of Texas At Austin
    The University Of Texas At Austin
    Electronic Noise
  • University Of South Florida
    University Of South Florida
    Computer Science

Frequently Asked Questions about Paul Colestock

What company does Paul Colestock work for?

Paul Colestock works for Midwest Microelectronics Consortium (Mmec)

What is Paul Colestock's role at the current company?

Paul Colestock's current role is A better starting point for the DoD and the Semiconductor Industry. Design driven from Atoms, to Assembly and AI..

What is Paul Colestock's email address?

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What schools did Paul Colestock attend?

Paul Colestock attended The University Of Texas At Austin, University Of South Florida.

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What skills is Paul Colestock known for?

Paul Colestock has skills like Semiconductors, Ic, Mixed Signal, Eda, Rf, Semiconductor Industry, Electronics, Cmos, Analog, Asic, Product Management, Wireless.

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