NOR Flash Array Characterization Leading to the World's First MLC Flash from 1992-1996. Work on each new generation of NOR MLC Flash from 1996 to 2004. In 2004, was the lead product engineer from Intel to join the IMFT JDP with Micron to develop MLC NAND Flash to help take IMFT flash from SLC in 2005 on 90nm to MLC NAND, sub 40nm in 2008. Starting in 2009, my focus shifted to SSDs using NAND Flash and now working on 3D-XPoint Technology and Products.My role prior to 2009 was primarily an extension of Technology Development to ensure MLC would function (program erase read algorithms and statistics) on end user products. Once products are well into the design phase, I turned my attention to manufacturing and product-level characterization and qualification. In 2009, I moved into SSDs, starting with integration of SSD system FW and NAND to create reliable, high performance products.

I was the lead product engineer from Intel to join the IMFT JDP chartered with quick delivery of world-class MLC NAND technology to market. This is a task for which I and several others within Intel won an Intel Acheivement Award in 2007.