Paul Lassa

Paul Lassa Email and Phone Number

ASIC Development Lead @ Applied Brain Research
California, United States
Paul Lassa's Location
San Francisco Bay Area, United States, United States
Paul Lassa's Contact Details

Paul Lassa personal email

n/a
About Paul Lassa

Assertive and resourceful engineering leader (what needs to get done? - and let's get to it!) in developing consumer products and cloud solutions. Technical strategy and project execution in embedded systems development, hardware, ASIC / SoC, and software, cloud integration. Performance, power, and cost-optimized devices, from concept through volume deployment, continuous provisioning. Deliver utility, performance, and craftsmanship in leadership electronic products, storage, and infrastructure.• Embedded processor System on Chip and Firmware / OS development in consumer electronics. Consumer and enterprise storage. Mobile/cloud applications design and development on iOS, android, alexa.• Creative, resourceful, and relentless, great problem solving skills, over 25 patents granted (https://sites.google.com/site/plpatents/)• Strong technical and leadership skills – with hands-on design and development.• Effective team management, project execution, schedule control, and cross-functional, global collaboration.Specialties: • System requirements, architecture, development, simulation, validation - ASIC, Hardware, Software.• ASIC and Firmware integration, performance, power management.• High-volume, cost-sensitive consumer product development and release to production.• NAND Flash memory, and SSD storage, SATA, PCIe, USB, ONFI, High-speed serdes, bus interfaces.• Chip and FPGA design flows, partner and vendor engagement.• Rapid prototyping, bring-up, debugging, and FA. PCB schematic, BOM, parts, DFT, DFM.• Mixed signal, RF, signal integrity, power integrity, thermal, EMI, ESD, regulatory compliance.

Paul Lassa's Current Company Details
Applied Brain Research

Applied Brain Research

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ASIC Development Lead
California, United States
Paul Lassa Work Experience Details
  • Applied Brain Research
    Asic Development Lead
    Applied Brain Research
    California, United States
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  • Ich
    Principal Engr., Ssd, Storage Design Consulting, Mobile App Design And Development
    Ich 2013 - Present
    Storage Systems Design Engineering, Platform analysis, solutions development, IP consulting• Storage System development, HW and FW architecture and requirements, customer/stakeholder engagement.• SSD performance, power optimization, workload, and implementation analysis.• Algorithm development, platform resource optimization.Application development - iOS, android, alexa; product, system, design, coding, IP, cloud integration; Cloud - AWS, Azure, Google Cloud, IBM Cloud:• EV (electric vehicle) and dining location reservation application, consumer and corporate.• Civic and Institutional Repair and Reporting app, with social media integration.• Food Health, Consumer nutrition resource, social shopping application.• Media and lifestyle–sharing application, social integration. Parse Platform.
  • Friend Software Corporation As
    Chief Product Officer
    Friend Software Corporation As 2017 - 2018
    Hillevåg, Rogaland, No
    • SMB, consumer cloud desktop and web applications platform. Team, workgroup collaboration, communications, workflow - cross-device, distributed deployment, on-prem and remote hosting. Open source, with commercial license and support model. Client, Server, webRTC-based video conferencing, applications and storage sharing.• Worked with Chief Architect, Technical leads, and customers to develop and document cloud platform, features, capabilities, product roadmap: Architecture, Product, Developers, Administration, User docs, and whitepapers.
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  • Friend Software Corporation As
    Advisor, Engineering Liaison
    Friend Software Corporation As 2015 - 2017
    Hillevåg, Rogaland, No
    Technology roadshow, evangelism. Customer, developer, partner engagement, presentations.Product prototype demo server and applications on AWS. Testing and debug of Videoconferencing client.
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  • Sandisk
    Sr. Manager, System Design Engineering, Consumer, Client Sata, Pcie Ssd, Usb, Cf Product Development
    Sandisk 2010 - 2012
    Milpitas, Ca, Us
    • Developed low-cost consumer and mid-range SATA SSD and Flash storage solutions.• Managed System Engineering team responsible for parallel new development and sustaining OEM support of consumer SSD and NAND modules, USB products, and CF, ATA card products. Collaboration with teams in Israel, India, Europe, and US.• Active in departmental planning, resource allocation, project coordination, and roadmap.• Managed system integration, verification, and qualification of 32nm / 24nm X2, eX3 memory transition.• Developed and specified SSD OS / driver functional and performance requirements and algorithms.• Validated features, performance, and endurance, gated release of final driver and tuned product configuration parameters. Bug, Issue tracking in JIRA.• Developed technical proposals and design partitioning for external partner collaborations for MLC / TLC (2, 3 BPC) NAND modules and Hybrid HDD / SSDs for consumer tablets and laptops.• Developed several patents on NAND device control Firmware, processing technologies, and power management in SSD systems.
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  • Sandisk
    Principal Engr., Ssd Architecture Group (Sata Ssd, Onfi Scalable Architecture)
    Sandisk 2009 - 2010
    Milpitas, Ca, Us
    • Engineer on SSD Architecture team responsible for product definition, system specifications, partitioning, performance estimates, and functional/performance modeling.• Development of ASIC MCP and firmware for MLC, TLC (2, 3 BPC) NAND management controller for modular / scalable SATA SSD.• Defined and developed system-level and internal functions between Front-End (SATA) to ONFI Host Interface controller (Marvell), SanDisk’s Flash channel controller, and SanDisk / Toshiba NAND.• Collaborated with FW team on development and bring-up of low-level flash channel driver.• SanDisk representative on the Open NAND Flash Interface (ONFI) Technical Committee, contributed to ONFI v2.3, v3.0+ next generation NAND interface.• Developed numerous patents on NAND device control Firmware, processing technologies, and power management in SSD systems.
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  • Sandisk
    Sr. Manager, Asic & Fpga Design Engineering (Sata / Pcie, Onfi, Usb, Sd / Mmc, Ms, Cf / Ata)
    Sandisk 2007 - 2009
    Milpitas, Ca, Us
    • SoC/ASIC Design Team Manager of controller Leads, and FPGA development team. Managed 15 direct reports and contractors, coordinated with SD-India design center to supplement local design capacity.• Co-managed multi-interface controller in-system validation effort / Accurev Issue tracking, dashboard. • Developed chip estimator/ parametric modeler (die-size, power) for silicon roadmap, IP, foundry planning, at 90nm, 65nm. Methodology and analysis utilized across controller line to meet critical power specs against variable IP/module/ECC/RAM vs. operating domain configurations.• Close collaboration with foundry qualification team to transition SoCs to TSMC / 90nmLP process and meet leakage, active current requirements of ultra-low-power flash storage devices for consumer portable electronics. Supported testing of wafer splits, characterization, and in-product controller characterization of Analog IP, logic, and RAM. • Preliminary development of SATA / PCIe flash controller project. SATA / PCIe, and USB PHY and MAC IP vendor reviews and design evaluations at 90nm.• Produced and presented ASIC Dept. controller weekly status to Corporate Engineering Product Line Managers and Exec. Staff.• Project launch and controller prototype development of new architecture for MLC / TLC (2, 3 BPC) NAND controller for modular / scalable SATA SSD / storage module.• Contributor to team effort of spec, definition, and development of modular Xilinx Virtex-based FPGA emulation platform PCB for all SoC designs. • Technical member of ASIC and Systems Patent Review committees.
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  • Sandisk
    Sr. Manager, Asic Design Engineering, Flash Storage Controllers (Usb, Sd / Mmc, Ms)
    Sandisk 2006 - 2007
    Milpitas, Ca, Us
    • ASIC design Team Leader developing multi-interface (USB, SD / MMC, MS) integrated controllers.• Managed 10 engineers on top-level design/integration team, Project direction/coordination with sub-module IP Team leads, cross-functional stakeholders and firmware teams in US, Israel, Europe, and India. • Created IP design requirements specification and managed weekly review of PHY IP provider and external physical design provider. • Delivered real-time, multi-processor embedded flash controller SoCs, including FPGA prototypes for OS/FW development, ASIC and card-level integration and verification, and chip production test vectors.• Developed power island architecture and design, ramped integrated verification/test methodology.• Delivered a highly functional Rev A controller for early firmware and software bring-up and product platform design verification.• Acute focus on design risk management to optimize overall cost of quality to meet rapid pace of product development cycles. • Led ASIC team on development of 20+ patent disclosures for SoC performance, power management, pad-ring, die packaging/bonding, and device production testing. Inventor or co-inventor on 8 disclosures.
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  • Sandisk
    Asic Design Manager Ii, Flash Storage Controllers (Usb, Sd/Mmc, Ms, Crypto)
    Sandisk 2005 - 2006
    Milpitas, Ca, Us
    • Program Manager / Technical Lead for multi-interface project, SoC development, integrating ASIC, Firmware, Hardware, component packaging, Test, and Product teams representing ~70% of engineering organization. Collaboration with design engineers in Israel, India, Europe, and US design centers. • Delivered real-time, multi-processor embedded flash controller SoCs, including FPGA prototypes for OS / FW development, ASIC and card-level integration and verification, and chip production test vectors.• Key contributor in requirements and architecture definition, collaboration with stakeholders in Firmware, System, Marketing, Standards, Packaging/substrate, and Production Qualification.• USB PHY IP evaluation, selection, digital and physical integration, qualification. USB MAC custom acceleration IP and FW. FIPS 140-2 Crypto Engine & physical countermeasures integration.• Hands-on and management for all ASIC design phases for several product generations, 6-9 month design cycles, multiple controllers in parallel development.• Developed engineering process flows for ASIC organization and achieved annual ISO9000 re-certification.
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  • Sandisk
    Asic Design Manager, Usb Flash Drives
    Sandisk 2003 - 2005
    Milpitas, Ca, Us
    • ASIC design and management of team to ship first generation SanDisk USB Flash drives. Led controller development for USB flash drive supporting SLC and MLC NAND. Worked closely with OS/Firmware team on product integration.• Developed and delivered additional foundry ports, as well as 2 successive product generations for ultra-low-cost, high-volume controllers.• Recruited, hired, and developed team for uC-based SoC design, IP integration, verification / ncsim, synthesis / Design Compiler, STA / Primetime, DFT, logic scan / ATPG, memory BIST, Formal / Logical Equivalence Check / LEC, backend integration / routing / timing closure / tapeout, silicon bring-up, driver/OS firmware integration, card-level testing, silicon characterization/qualification, release to production, sustaining production engineering, and F/A.
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  • Tla
    Sr. Asic & Sys. Sw Engineer
    Tla 2000 - 2003
    • Designed and developed a prototype wireless communications device and network infrastructure.• Wireless handset, basestations with transmit/receive, mod/demod (VCO, Mixer, PA, LNA, IF Amp, PLL).• Network Router prototype modeling (C++), design (Verilog). Queue management and routing relation development.
  • Stanford University
    Sr. R&D Engineer, Hardware Engineering
    Stanford University 1996 - 1999
    Stanford, Ca, Us
    • Team developed a key subsystem of Stanford’s Gravity Probe B Relativity Project, a NASA-sponsored satellite physics mission, with flight electronics and spacecraft manufactured by Lockheed Martin. Launched from Vandenberg AFB in April, 2004. einstein.stanford.edu• Specified, designed, and managed development of Actel RAD hard FPGAs and 6 digital subsystem PCBs, a comm. channel (GFAB), and system SW for GP-B’s Gyroscope Suspension System (GSS).• Developed backplane, system architecture, managed prototyping, design reviews, release to manufacturing. 7-ch A/D, D/A, DSP processing.• Managed 5 engineers, 2 technicians, initiated lab facility set-up, equipment and tools acquisition, and vendor negotiations.
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  • The 3Do Company
    Sr. Asic And Fpga Design Engineer
    The 3Do Company 1994 - 1996
    Us
    • Responsible for logic design/verification of storage peripheral and graphics products.• Joint development of 3D Graphics Engine (Direct3D) SoC for add-in PC Graphics card. Design Spec. of AGP / PCI Bus controller. • Designed and implemented Tacoma PCI controller/bridge LPGA / ASIC for PCI to PowerBus graphics controller. Bring-up of pilot build on Intel platform. Verified multi-vendor PCI card functional compatibility.• Implemented CD-ROM controller ASIC (MEC, TI, LG Semi. ports) for Videogame system. Prototyped in Xilinx FPGA.
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  • Magicvideo Technology
    Sr. Hardware Project Engineer – Led Imagewall Display
    Magicvideo Technology 1993 - 1994
    • Developed workstation-based controller for Video and Graphics LED ImageWall Display. Hardware system provided video and computer-graphics Gamma-correction, and programmable brightness, contrast, and color mixing for Billboard-sized Jumbo Screen.• Hired and managed 2 Software Engineers for initial prototype. Conducted preliminary FCC testing.
  • Commodore Amiga Computers
    Sr. Engineer, Asic Design, Pcb Hardware Design
    Commodore Amiga Computers 1988 - 1993
    Us
    • Design Lead and Project Engineer, Amiga 4000T MC68040/060 Tower/SCSI. Schematic capture, 6-layer SMT motherboard, mech. integration, specs, BOM, FCC compliance, Pilot Production. Prototype bring-up and OS integration with NCR SCSI-2 controller. • Designed DMAgic Controller and Graphics Blitter / Accelerator ASIC and PCB motherboard for consumer home computer.
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  • Timeworks, Inc.
    Software Engineer
    Timeworks, Inc. 1982 - 1984
    • Leading consumer software publisher of desk top publishing, tax preparation, word processing, personal finance, speed reading, education, and entertainment.• Primary Software Engineer for 4 released titles.

Paul Lassa Skills

Leadership Embedded Software Systems Design Development Hardware Architecture Engineering Management Requirements Analysis Computer Architecture Linux System On A Chip Algorithms Debugging Integrated Circuits Functional Verification Matlab Arm Pcb Design Pcie Asic Sata System Design Vlsi Verilog Team Leadership Solutions Usb Ssd Xcode Swift Mobile Applications C (Programming Language Ios Development Mixed Signal Embedded Systems Android Nand Flash Program Management Cross Functional Team Leadership Fpga Soc Continuous Integration Electrical Engineering C++ Storage Nand Software Engineering Python Hardware Management Semiconductors Simulations Project Management Firmware Product Development Design Performance Analysis Software Development Static Timing Analysis Device Drivers Rtos Patents Cloud Computing Application Specific Integrated Circuits Field Programmable Gate Arrays Integration Flash Memory Object Oriented Design System Architecture

Paul Lassa Education Details

  • Stanford University
    Stanford University
    Electrical & Computer Engineering
  • University Of Illinois Urbana-Champaign
    University Of Illinois Urbana-Champaign
    Electrical & Computer Engineering

Frequently Asked Questions about Paul Lassa

What company does Paul Lassa work for?

Paul Lassa works for Applied Brain Research

What is Paul Lassa's role at the current company?

Paul Lassa's current role is ASIC Development Lead.

What is Paul Lassa's email address?

Paul Lassa's email address is pl****@****bal.net

What is Paul Lassa's direct phone number?

Paul Lassa's direct phone number is +140880*****

What schools did Paul Lassa attend?

Paul Lassa attended Stanford University, University Of Illinois Urbana-Champaign.

What are some of Paul Lassa's interests?

Paul Lassa has interest in Children, Environment, Education, Poverty Alleviation, Science And Technology, Health.

What skills is Paul Lassa known for?

Paul Lassa has skills like Leadership, Embedded Software, Systems Design, Development, Hardware Architecture, Engineering Management, Requirements Analysis, Computer Architecture, Linux, System On A Chip, Algorithms, Debugging.

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