Paul Lassa Email & Phone Number

California, United States

• Storage Systems Design Engineering, Platform analysis, solutions development, IP consulting
• Storage System development, HW and FW architecture and requirements, customer/stakeholder engagement.
• SSD performance, power optimization, workload, and implementation analysis.
• Algorithm development, platform resource optimization.Application development - iOS, android, alexa; product, system, design, coding, IP, cloud integration; Cloud - AWS, Azure, Google Cloud, IBM Cloud:
• EV (electric vehicle) and dining location reservation application, consumer and corporate.
• Civic and Institutional Repair and Reporting app, with social media integration.

Hillevåg, Rogaland, NO

• SMB, consumer cloud desktop and web applications platform. Team, workgroup collaboration, communications, workflow - cross-device, distributed deployment, on-prem and remote hosting. Open source, with commercial.
• Worked with Chief Architect, Technical leads, and customers to develop and document cloud platform, features, capabilities, product roadmap: Architecture, Product, Developers, Administration, User docs, and whitepapers.

Hillevåg, Rogaland, NO

Technology roadshow, evangelism. Customer, developer, partner engagement, presentations.Product prototype demo server and applications on AWS. Testing and debug of Videoconferencing client.

Milpitas, CA, US

• Developed low-cost consumer and mid-range SATA SSD and Flash storage solutions.
• Managed System Engineering team responsible for parallel new development and sustaining OEM support of consumer SSD and NAND modules, USB products, and CF, ATA card products. Collaboration with teams in Israel, India.
• Active in departmental planning, resource allocation, project coordination, and roadmap.
• Managed system integration, verification, and qualification of 32nm / 24nm X2, eX3 memory transition.
• Developed and specified SSD OS / driver functional and performance requirements and algorithms.
• Validated features, performance, and endurance, gated release of final driver and tuned product configuration parameters. Bug, Issue tracking in JIRA.

Milpitas, CA, US

• Engineer on SSD Architecture team responsible for product definition, system specifications, partitioning, performance estimates, and functional/performance modeling.
• Development of ASIC MCP and firmware for MLC, TLC (2, 3 BPC) NAND management controller for modular / scalable SATA SSD.
• Defined and developed system-level and internal functions between Front-End (SATA) to ONFI Host Interface controller (Marvell), SanDisk’s Flash channel controller, and SanDisk / Toshiba NAND.
• Collaborated with FW team on development and bring-up of low-level flash channel driver.
• SanDisk representative on the Open NAND Flash Interface (ONFI) Technical Committee, contributed to ONFI v2.3, v3.0+ next generation NAND interface.
• Developed numerous patents on NAND device control Firmware, processing technologies, and power management in SSD systems.

Milpitas, CA, US

• SoC/ASIC Design Team Manager of controller Leads, and FPGA development team. Managed 15 direct reports and contractors, coordinated with SD-India design center to supplement local design capacity.
• Co-managed multi-interface controller in-system validation effort / Accurev Issue tracking, dashboard.
• Developed chip estimator/ parametric modeler (die-size, power) for silicon roadmap, IP, foundry planning, at 90nm, 65nm. Methodology and analysis utilized across controller line to meet critical power specs against.
• Close collaboration with foundry qualification team to transition SoCs to TSMC / 90nmLP process and meet leakage, active current requirements of ultra-low-power flash storage devices for consumer portable electronics..
• Preliminary development of SATA / PCIe flash controller project. SATA / PCIe, and USB PHY and MAC IP vendor reviews and design evaluations at 90nm.
• Produced and presented ASIC Dept. controller weekly status to Corporate Engineering Product Line Managers and Exec. Staff.

Milpitas, CA, US

• ASIC design Team Leader developing multi-interface (USB, SD / MMC, MS) integrated controllers.
• Managed 10 engineers on top-level design/integration team, Project direction/coordination with sub-module IP Team leads, cross-functional stakeholders and firmware teams in US, Israel, Europe, and India.
• Created IP design requirements specification and managed weekly review of PHY IP provider and external physical design provider.
• Delivered real-time, multi-processor embedded flash controller SoCs, including FPGA prototypes for OS/FW development, ASIC and card-level integration and verification, and chip production test vectors.
• Developed power island architecture and design, ramped integrated verification/test methodology.
• Delivered a highly functional Rev A controller for early firmware and software bring-up and product platform design verification.

Milpitas, CA, US

• Program Manager / Technical Lead for multi-interface project, SoC development, integrating ASIC, Firmware, Hardware, component packaging, Test, and Product teams representing ~70% of engineering organization..
• Delivered real-time, multi-processor embedded flash controller SoCs, including FPGA prototypes for OS / FW development, ASIC and card-level integration and verification, and chip production test vectors.
• Key contributor in requirements and architecture definition, collaboration with stakeholders in Firmware, System, Marketing, Standards, Packaging/substrate, and Production Qualification.
• USB PHY IP evaluation, selection, digital and physical integration, qualification. USB MAC custom acceleration IP and FW. FIPS 140-2 Crypto Engine & physical countermeasures integration.
• Hands-on and management for all ASIC design phases for several product generations, 6-9 month design cycles, multiple controllers in parallel development.
• Developed engineering process flows for ASIC organization and achieved annual ISO9000 re-certification.

Milpitas, CA, US

• ASIC design and management of team to ship first generation SanDisk USB Flash drives. Led controller development for USB flash drive supporting SLC and MLC NAND. Worked closely with OS/Firmware team on product.
• Developed and delivered additional foundry ports, as well as 2 successive product generations for ultra-low-cost, high-volume controllers.
• Recruited, hired, and developed team for uC-based SoC design, IP integration, verification / ncsim, synthesis / Design Compiler, STA / Primetime, DFT, logic scan / ATPG, memory BIST, Formal / Logical Equivalence Check.

• Designed and developed a prototype wireless communications device and network infrastructure.
• Wireless handset, basestations with transmit/receive, mod/demod (VCO, Mixer, PA, LNA, IF Amp, PLL).
• Network Router prototype modeling (C++), design (Verilog). Queue management and routing relation development.

Stanford, CA, US

• Team developed a key subsystem of Stanford’s Gravity Probe B Relativity Project, a NASA-sponsored satellite physics mission, with flight electronics and spacecraft manufactured by Lockheed Martin. Launched from.
• Specified, designed, and managed development of Actel RAD hard FPGAs and 6 digital subsystem PCBs, a comm. channel (GFAB), and system SW for GP-B’s Gyroscope Suspension System (GSS).
• Developed backplane, system architecture, managed prototyping, design reviews, release to manufacturing. 7-ch A/D, D/A, DSP processing.
• Managed 5 engineers, 2 technicians, initiated lab facility set-up, equipment and tools acquisition, and vendor negotiations.

US

• Responsible for logic design/verification of storage peripheral and graphics products.
• Joint development of 3D Graphics Engine (Direct3D) SoC for add-in PC Graphics card. Design Spec. of AGP / PCI Bus controller.
• Designed and implemented Tacoma PCI controller/bridge LPGA / ASIC for PCI to PowerBus graphics controller. Bring-up of pilot build on Intel platform. Verified multi-vendor PCI card functional compatibility.
• Implemented CD-ROM controller ASIC (MEC, TI, LG Semi. ports) for Videogame system. Prototyped in Xilinx FPGA.

• Developed workstation-based controller for Video and Graphics LED ImageWall Display. Hardware system provided video and computer-graphics Gamma-correction, and programmable brightness, contrast, and color mixing for.
• Hired and managed 2 Software Engineers for initial prototype. Conducted preliminary FCC testing.

US

• Design Lead and Project Engineer, Amiga 4000T MC68040/060 Tower/SCSI. Schematic capture, 6-layer SMT motherboard, mech. integration, specs, BOM, FCC compliance, Pilot Production. Prototype bring-up and OS integration.
• Designed DMAgic Controller and Graphics Blitter / Accelerator ASIC and PCB motherboard for consumer home computer.

• Leading consumer software publisher of desk top publishing, tax preparation, word processing, personal finance, speed reading, education, and entertainment.
• Primary Software Engineer for 4 released titles.

Ms, Electrical & Computer Engineering

Bs, Electrical & Computer Engineering