Design and production of power IGTO devices.

Created technology strategy with Sr. VP of Analog business unit, VP of Analog Design, VP of Analog Marketing and the CEO.Presented monthly roadmap status to Sr. VP of Analog business unit, VP of Analog Design, VP of Analog Marketing and the CEO.Managed 14-person engineering team that supported 12 core production processes amounting to ~400 production routes.Led the engineering team responsible for design rule testing and documentation.Led the engineering team responsible for model extraction and PDK implementation. Designed, simulated, and optimized 0.35 um NCH and PCH LDMOS with maximum operating voltage of 16, 18, 35, 45, 60, and 75 V. The gate charge and FOM are in the 90th percentile of foundry processes. The specific on resistance outperformed an external BCD 0.18 um process by more than 10%. Vetted external foundry BCD processes.Supervised internal adaptation and customization of external foundry PDK for analog design team.Identified and remedied external foundry device issues by guiding external process engineering and guiding internal design and product engineering.

Managed engineering development and production support team for BCD 2.0 um and 0.5 um processes.Designed and simulated (Atlas and Athena) BCD 2.0 um 150 V 2.0 um PCH with 150 V gate oxide.Designed and simulated (Atlas and Athena) BCD 0.5 um process consisting of: VNPN (3 and 6 GHz), VPNP (500 MHz), NLDMOS 24 V, 50 V, 150 V, PLDMOS 150 V, and DENMOS 16 V.Created device optimization layouts and model extraction test patterns for a BCD 0.5 um process.

BCD 0.5 um device development and Light Valve (Liquid Crystal on Silicon) development