Paul Meaney Email & Phone Number

Vancouver, British Columbia, Canada

Working on Pre Silicon Validation of cutting edge networking silicon products.Use Systemverilog and UVM to create flexible, reusable verification testbenches to ensure high quality, bug and error free RTL.My responsibilites in this role include:Coding complex testbench components in Systemverilog, following the UVM framwork.Designing and owning test plans.Debugging RTL and DV code.Supporting Tools and Infrastructure, including Validation model compilations, volume test regression management, UNIX environment management and automation scripting.Some of my key skills are:UVM methodology.SystemVerilog language.UNIX system and configuration.Test plan design.Python Scripting.Git.

Shannon

Pre - Silicon verification of cutting edge hardware accelerators and chipsets.

Shannon

Part of silicon RTL design team. Design and test logic circuits using hardware description language, (SystemVerilog).

Ennis

Advised customers on a wide range of electrical products, completed transactions and provided device tutorials.

Galway

Assisted engineering officers in their duties, including the design of new and existing electric HV and MV transmission lines.

Ennis

Advise customers on suitable call plans and handsets. Process new contracts. Provide device set up and trouble shooting.

Bachelor’S Degree, Electronic And Computer Engineering

FYP: DSP, audio processing on FPGAs interfaced with a Python GUI

Leaving Certificate