Paul Muller

Paul Muller Email and Phone Number

Founder and Managing Director @ Aptimus Technology
Lausanne, VD, CH
Paul Muller's Location
Lausanne Metropolitan Area, Switzerland, Switzerland
Paul Muller's Contact Details

Paul Muller personal email

n/a
About Paul Muller

I am a passionate and results-driven senior executive and engineering and business consultant. I try to approach new challenges with curiosity and a learning mindset, and to address them with analytical methodologies and cognitive awareness on one side, results focus and can-do attitude on the other. I use my business acumen, my market understanding, and my technology expertise to deliver time and again, bringing out the best in everyone through my ability to listen and build a shared vision.Multi-lingual and culturally agile serving startups, SMEs and Tier-1 high-growth multinationals, my preferred challenges are building or re-building high-performance teams for sustained business success and providing strategy and engineering consulting services to help organizations achieve short-term impact and long-term value creation.

Paul Muller's Current Company Details
Aptimus Technology

Aptimus Technology

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Founder and Managing Director
Lausanne, VD, CH
Website:
aptimustech.com
Paul Muller Work Experience Details
  • Aptimus Technology
    Founder And Managing Director
    Aptimus Technology
    Lausanne, Vd, Ch
  • Aptimus Technology
    Ceo And Founder
    Aptimus Technology
    Lausanne, Vd, Ch
  • Aptimus Technology
    Founder
    Aptimus Technology Nov 2024 - Present
  • Deeplight
    Ceo/Coo
    Deeplight Aug 2024 - Present
    Saint Sulpice, Vaud, Ch
  • Em Microelectronic
    Vice President Of Development
    Em Microelectronic Apr 2021 - Jul 2024
    Marin, Ch
    As a member of EM's executive team, I was responsible for corporate product strategy, development and go-to-market of all ICs, leading >150 FTEs across six sites on two continents. To prepare EM's engineering teams for the challenges of the future in a changing world and build a competitive organization, together with the Development leadership team we• Deployed Agile methodology across software, hardware, and engineering leadership teams, enabling the organization to adapt quickly to fast-changing market conditions• Built a cross-product-line SoC Platform and IP team serving multiple business lines, reducing engineering cost and accelerating time-to-market for new developments• Initiated dedicated Product Engineering and Product Management activities to support organizational growth, improving product quality and product definition• Proposed implementation of OKR methodology to provide visibility and alignment and focus change initiatives, improving organizational visibility and alignment
  • Em Microelectronic
    Rfid Business Unit Manager
    Em Microelectronic Mar 2017 - Apr 2021
    Marin, Ch
    Leading the RFID organization with full P&L responsibility and ownership of strategy, product roadmap, partnership development, technical marketing, product management (including NPI/GTM) and R&D.Achievements• Market introduction of paradigm-shifting RAINFC dual-frequency em|echo product line, leading the market in consumer engagement and brand protection applications• Turned around the RFID business resulting in 15% CAGR• Received multiple prestigious product and innovation awards and a regular speaker at industry events
  • Em Microelectronic
    Bu Technical Leader Rfid
    Em Microelectronic Jan 2015 - Feb 2017
    Marin, Ch
    Technical leadership (20+ people across three sites in EU and US) for LF, UHF and dual-frequency HF/UHF RFID product lines including design, layout, project management, test engineering, product support and FAEs
  • Rain Rfid Alliance
    Board Member
    Rain Rfid Alliance Apr 2021 - Mar 2023
    Cranberry Township, Pa, Us
    Board of Directors for the RAIN Alliance
  • Rain Rfid Alliance
    Chair Smart Products Workgroup
    Rain Rfid Alliance Mar 2018 - Mar 2021
    Cranberry Township, Pa, Us
  • Rain Rfid Alliance
    Member Smart Products & Packaging Workgroup
    Rain Rfid Alliance Mar 2017 - Mar 2018
    Cranberry Township, Pa, Us
  • Mead Education Sa
    Lecturer
    Mead Education Sa 2017 - 2018
    St-Sulpicde, Ch
    Lecturing on practical issues in wireless transceiver design
  • Mediatek
    Senior Technical Manager Rf Design
    Mediatek Feb 2010 - Dec 2014
    Hsin-Chu, Tw
    2014 - 2014 Senior Technical Manager RF Design2010 - 2013 Senior Staff RFIC Design EngineerProjects:• Transmit path design team leader for the Mediatek's first LTE-A R11 transceiver MT6176, supporting LTE FDD/TDD R11 Cat-6 with 2x CA, DC-HSPA+, TD-SCDMA, EDGE, CDMA2000 1x/EVDO Rev. A (SRLTE)http://www.mediatek.com/en/products/mobile-communications/smartphone1/mt6750• Receiver design team leader for Mediatek's first 3.75G/HSPA+ transceiver MT6280, a single-chip DC-HSUPA thin-modem SoC with receive diversity• Receiver design & transceiver verification leader for 2G/TD-SCDMA transceiver MT6163
  • Marvell Semiconductor
    Senior Mixed-Signal Ic Design Engineer
    Marvell Semiconductor Aug 2006 - Jan 2010
    Santa Clara, Ca, Us
    Design of analog baseband circuits and data converters for highly integrated wireless transceivers (WiFi/WiMax, FM, GPS) in advanced CMOS technologies. In particular contribution to Marvell's 55nm Avastar multi-radio connectivity product line including 88W8787, 88W8788 and 88W8790:http://www.linleygroup.com/newsletters/newsletter_detail.php?num=683
  • Ecole Polytechnique Federale De Lausanne
    Research Assistant
    Ecole Polytechnique Federale De Lausanne Jul 2002 - Jul 2006
    Ph.D. research on advanced CMOS fiber-optic receivers for short-distance communications.- Design of a high-speed optical receivers, including transimpedance amplifier, limiting amplifier, clock and data recovery- Development of a specification-driven top-down design approach using mathematical and behavioral modeling of high-speed optical receivers and clock recovery circuits in particular- Lab testing and characterization of all receiver building blocks. Experience in jitter testing, eye diagram and BER measurement.- Experience in chip assembly and foundry interaction. In-depth knowledge on design issues in sub-100nm CMOS processes- Teaching assistant for semester and master projectsFurthermore in charge of:- establishing a high-speed measurement lab environment- the foundry interface for process selection and tape-outs
  • Xemics Sa
    Mixed-Signal Ic Design Engineer
    Xemics Sa Apr 1999 - Jun 2002
    Specification, design and test of low-power analog circuits for high-accuracy sensing and data acquisition applications- switched-capacitor circuit design- design, lab characterization and production transfer of sensor interface circuit for industrial data acquisition applicaitons- system-level verification of mixed-signal SoC- profound interaction with customers during all phases of the product development, from specification to the transfer to volume production

Paul Muller Skills

Mixed Signal Semiconductors Analog Ic Cmos Rf Soc Wireless Eda Integrated Circuit Design Team Leadership Analog Circuit Design Integrated Circuits Asic Mixed Signal Ic Design Radio Frequency Signal Processing Wireless Technologies Chipset Silicon Low Power Design Cadence Virtuoso Cellular Communications Sensors Electronics Vlsi System On A Chip Rfid+ Project Management Testing Change Management Lte Analog And Mixed Signal Modeling And Verification Analog Rf And Mixed Signal Ic Design Chip Integration Design Methodology Rf Design Business Strategy Organizational Leadership Rfid Radio Frequency Identification

Paul Muller Education Details

  • Epfl
    Epfl
    Electrical Engineering
  • Fsrm
    Fsrm
    General
  • Hemsley-Fraser
    Hemsley-Fraser
    Organizational Leadership
  • Epfl
    Epfl
    Electrical Engineering
  • Athénée De Luxembourg
    Athénée De Luxembourg
    Mathematics And Physics

Frequently Asked Questions about Paul Muller

What company does Paul Muller work for?

Paul Muller works for Aptimus Technology

What is Paul Muller's role at the current company?

Paul Muller's current role is Founder and Managing Director.

What is Paul Muller's email address?

Paul Muller's email address is pa****@****epfl.ch

What schools did Paul Muller attend?

Paul Muller attended Epfl, Fsrm, Hemsley-Fraser, Epfl, Athénée De Luxembourg.

What skills is Paul Muller known for?

Paul Muller has skills like Mixed Signal, Semiconductors, Analog, Ic, Cmos, Rf, Soc, Wireless, Eda, Integrated Circuit Design, Team Leadership, Analog Circuit Design.

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