Paul Wilcox Email and Phone Number

Sr. Manager of organization developing IP and ASIC solutions for Amazon Lab126 devices. Manage teams of architects, RTL designers, design verification and ASIC implementation engineers developing ASICs and IPs including the Amazon AZ1 Neural Edge Processor.

Interim general manager of 200 person multisite program management, debug and analytics group. Led the Engineering Portfolio Management team focused on emerging technology products. Led efforts to optimize organization to eliminate inefficiencies and accelerate the time to market. Investigations of machine learning and data analytics in design automation and optimization.

Lead a world-class team of analog/mixed-signal verification product engineers that deliver proven high-value AMS verification functionality to AMS verification engineering and field application engineering for rapid customer deployment. The group’s scope includes circuit verification, mixed-signal verification, circuit characterization, connections to adjacent flows (including digital verification and physical verification) for analog ICs, analog/mixed-signal ICs, digital/mixed-signal ICs, and memory ICs. The group’s responsibilities include everything from problem identification through deployment to early adopters to finished production product with deployment tools for rapid customer ramp-up.

Lead a worldwide, world-class team of analog/mixed-signal verification engineers that provide superior Analog FastSPICE Platform (AFS) technical engagement for target accounts, including: technical engagement strategy development, technical qualification, evaluations, proliferation campaigns, customer training, new technology deployment, and non-routine support. The team is responsible for helping the AMS Verification Business Unit (AVBU) meet its business objectives.

Responsible for worldwide applications, customer support, and services for Berkley Design Automation's Analogy FastSPICE nanometer circuit verification platform for analog, RF, mixed-signal, and custom digital circuits.

Engineering Product Manager for Tegra Mobile Products. Responsible for engineering management including product definition, architecture, design, development, manufacturing and launch of phone and tablet platform products based on Tegra Mobile Processor.• Product Manager for go to market activities for NVidia Tesla Supercomputing GPUs for high performance computing and cloud servers.• Engineering Product Manager for NVidia Notebook products responsible for entire product lifecycle from product definition, roadmaps, design, manufacturing, launch and sustaining

Led the engineering organization of LocoLabs, a product design services company specializing in digital multimedia, internet and consumer products. Hired to increase the organizations productivity and develop a line of company owned products and IP. Responsible for managing 20 engineers, writing project bids, negotiating contracts, managing customer interfaces, managing multiple budgets, schedules and personnel. Oversee and actively participate in tasks including system architecture, ASIC development, PCB design, software design, mechanical, power and cooling design. Member of senior executive staff developing strategies and directing short-term and long-term projects.

Responsible for the verification automation and testbench product lines of the Cadence Incisive verification platform. Managed three groups in the product line. Developed a strategy for addressing verification automation for the HDL designer market. Created a business plan and received funding for a new product line. • Built and managed a cross functional team of 15 experts throughout the world. Successfully released the Incisive SoC Verification Flow on schedule in June 2004 and the Incisive Designer Verification Flow on schedule in January 2005. Led development of technical messaging of Cadences Incisive verification platform. Architected and evangelized the Cadence Unified Verification Methodology Authored the text “Professional Verification, A Guide to Advanced Functional Verification” detailing the Cadence Unified Verification Methodology and its uses.

Architected and designed part of the Performance Route Processor linecard for the GSR router. Met all development milestones and used advanced techniques to support a lower-cost FPGA . Architected and designed linecard system interfaces including Smart Card, NVRAM, interrupt control, power and MBUS interfaces utilizing a low-cost FPGA. .• Led team of engineers verifying a Gigabit Ethernet IC for a GSR router lincard under extreme budget and time to market pressure. Met all schedule and resource goals utilizing offshore resources and FPGA prototype.

Productized the industry’s first Assertion-Based Verification solution working with key customers and technologists to develop tool use model.

Architected and designed ASICs for Sun workstations including bus interface units, graphics engines, datapath switches, system controllers, and DMA engines. Performed development tasks in creation of ASICs for workstations including synthesis, timing analysis, place and route, verification, design for test and debug.