Pavan Kumar Bajjuri Email & Phone Number

Pavan Kumar Bajjuri is a Hardware Logic Design Co-op @ Intel | DFT Intern @ AMD, San Jose | TA for Electronics Laboratory | ISA for Microprocessor System Design | Masters in EE @ SJSU | Bachelors from National Institute of Technology Delhi IND at Intel Corporation. Colleagues describe them as "Pavan Kumar Bajjuri stood out among his peers in my Advanced Digital System Design and Synthesis class (EE:271) during the Spring 2023 semester, earning an outstanding grade. With a solid understanding of RTL Design, Static Timing Analysis (STA), FSMs, Logic synthesis, and Power Analysis and a passion for excellence, Pavan consistently showcased his abilities through exceptional performance in assignments, exams, and the successful implementation of the 5 Stage MIPS Pipelined Processor on the FPGA Project. His unwavering dedication, commitment, and goal-oriented mindset make him an invaluable addition to any organization fortunate enough to have him on board."