Pavan S Email & Phone Number

A budding VLSI engineer , working as a Senior Engineer at SmartSoC Solutions Pvt Ltd. I have completed Master's degree in VLSI DESIGNS from Manipal School of Information Sciences, Manipal in May 2020.AREA OF INTERESTRTL Design and Verification, SOC Verification.TECHNICAL SKILLSLanguages : Verilog, System Verilog , Shell Script, Perl and C.Tools Known : Xilinx ISE, Questa Sim, Cadence Virtuoso and Cadence NC Launch. Methodologies : UVM.Operating systems : Linux, Windows.PROJECTS1. Functional Verification of DDR2 SDRAM.ACADEMIC PROJECTS1. Design and Analysis of Low Power Multiplier Circuits Using FinFets.2. Design and Verification of Constant Convolution.3. Vehicle monitoring system based on RFID.4. Pedestrians guide based on ARM.