- RTL Design & Micro Architecture.- RTL for the High Speed Ethernet Subsystem.- Constraints Management.- High Speed Ethernet Sub System- IEEE 802.3 STD.

- Worked on Full Chip Cycle.- Collaborate with FW teams on defining/improving the performance based HW design.- Working closely with PD Teams on the timing closure, floor plan.- Defining Constraints at the Subsystem level.- Key contribution towards resolving the customer issues.- subsystem level micro-architecture.- power domain partitioning using low power techniques.- Worked on UWB std.- RTL Design for Encoders/Decoders.

- RTL Coding for the Base Band Subsystem.- State machines Design.- DSP/ARM Integration.- Register Management.- Working with FW to define the new feature based on Market & Customer Needs.- SoC Integration.- Memory management between DSP and ARM Subsystems.

- SoC Integration- Working with Cross Functional Teams and support on the bring up.- RTL Design.- Static Checks at the SoC Level.

RTL, Spyglass Lint/CDC on SoC.LEC checking.

Design and Development of Avionics Full Duplex Ethernet Switch (AFDX)- ARINC 664 P7.> Gained knowledge on Development of FPGA based IP design and Development.> RTL coding in VHDL also creating test bench for the corresponding block.> Simulation and Debugging of test cases using Xilinx ISim simulator.> Debug with Chip Scope analyzer.> expert in development of State Machines in VHDL.> DO-254 style of RTL coding.

>Semiconductor testing with Lab VIEW.> Lab VIEW based application development.> FPGA firmware debug and testing the device according to that.> Memory characterization on bench. >Validation of memory devices.>Applying different test conditions and generating data from that.>creating spec and memo's.>Verilog programming for digital design.