Parth Deshpande is a DRAM Design Engineer at Micron Technology.
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Dram Design EngineerMicron TechnologyMadison, Wi, Us -
Graduate Research AssistantUniversity Of Wisconsin-Madison Jan 2024 - PresentMadison, Wisconsin, United StatesCOMPUTE LabUnder Prof Akhilesh Jaiswal- Surveyed technologies beyond the current von Nuemann Architecture to achieve results in applications of Extreme Edge Hardware for AI, Neuromorphic Computing, Optical Computing- Designed a low delay sense amplifier with a high bandwidth of >10GHz to support read operations for Optical SRAMs- Demonstrated in-memory computing using the sense amplifier on Cadence with power, delay, and process variation considerations -
Graduate Teaching AssistantUniversity Of Wisconsin-Madison Jan 2024 - Jun 2024Madison, Wisconsin, United StatesPhysics 208 - Electrostatics, Magnetism Optics, and Modern Physics- Responsible for supervising lab work and discussion hours for a cohort of 60 students- Conducted extra office hours and problem solving sessions to help students understand concepts of Physics more effectively -
Graduate Research AssistantUniversity Of Wisconsin-Madison Aug 2023 - Dec 2023Madison, Wisconsin, United StatesWide Bandgap Materials and Devices GroupUnder Prof Chirag Gupta - Utilized in-depth understanding of device physics and materials in Wide BandGap III-V compounds and carbon nanotubes to fabricate semiconductor devices for high-frequency applications- Fabricated and measured RF devices in the UW Madison Cleanroom facility with feature lengths of less than 200 nanometers with tools including Laser Writer, Thermal Evaporator, ALD, E-Beam Lithography, SEM- Designed the photo mask for electron beam/optical lithography of GaN HEMTs using KLayout GDSII software -
Dram EngineerMicron Technology May 2024 - Aug 2024Boise, Idaho, United States -
Hardware EngineerQualcomm Jul 2022 - Jul 2023Experience in methodologies for RTL design and automation of System on Chip using VHDL, Verilog, System Verilog, and Python- Automated the task of taking input parameters to configuration files of different SoCs from Excel Sheet - Worked on tool flows for clock domain crossing, low power supply, static timing analysis, synthesis of several SoCs- Optimized the number of power retention flip flops from 76% to 24% after power collapse to have efficient power consumption- Developed a firmware for fast charging technology to identify the adaptability of source and sink faster- Worked on pipelining the input and output modules of a SoC to meet setup and hold time requirements -
InternQualcomm Jan 2022 - Jun 2022Bangalore Urban, Karnataka, India -
Summer InternIndian Institute Of Technology, Bombay May 2022 - Jul 2022- Worked on modeling discrete electronic devices for developing a new software eSim- Added SPICE models for MOSFETs, diodes, BJTs, and Power Transmission Lines to the software for simulation- Developed SPICE models for other devices like Gunn Diode compatible with the software by modifying the pre-existing Python and json files
Parth Deshpande Education Details
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Jog Education Trusts P. Jog College Of Science & Commerce, Mayur Colony ,Kothrud, . Pune 411 038.90.5% -
Abhinav Vidyalaya English Medium School, Pune91.2%
Frequently Asked Questions about Parth Deshpande
What company does Parth Deshpande work for?
Parth Deshpande works for Micron Technology
What is Parth Deshpande's role at the current company?
Parth Deshpande's current role is DRAM Design Engineer.
What schools did Parth Deshpande attend?
Parth Deshpande attended University Of Wisconsin-Madison, Birla Institute Of Technology And Science, Pilani, Jog Education Trusts P. Jog College Of Science & Commerce, Mayur Colony ,kothrud, . Pune 411 038., Abhinav Vidyalaya English Medium School, Pune.
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