Staff Engineer, Manager - Processor Architecture Modelling
CurrentLeading Processor Simulator development and integration for RISC-V, ARMv7, Renesas and PowerPC architectures including Fast and approximate ISA modeling with microarchitecture and architecture details like pipelining, MPU, MMU, Cache (L1/L2), HW-SW Exceptions, FPU modeling etc. Leading methodology and performance initiatives for ASIP IA modelling, parallel multi-threaded & host based simulation, Just in Time and binary translation. Close engagement with global Automotive and AI customers for hardware platform and software bring ups. Responsible for Autosar and FreeRTOS OS bring ups on automotive virtual platforms. Involved in all stages of software lifecycle from requirement gathering onwards.Undertook infrastructural utilities around dynamic clock and reset handling, interrupt analysis, JIT Cache probing, simulation run control etc. Responsible for various debugger integration of Third party ISS into SystemC based Synopsys Virtualizer environment like ADL models from NXP including PowerPC Cores and DSP accelerator models, CEVA DSP models, RISC-V models, that includes implementing C++ based instrumentation and run control details.Support feature development on SystemC Generic Infrastructure IP modelling library and briefly supported SystemC models for ARM Prime cell IPs.
