Pedram A. Riahi Email & Phone Number

Burlington, Ma, Us

Burlington, Ma, Us

Arlington, Va, Us

Arlington, Va, Us

Arlington, Va, Us

■ Member of the FPGA Verification and Embedded Processing Section in the Radar Controls and Electronics Department of the Electrical Design Directorate at Raytheon IDS Headquarter.■ Raytheon Six Sigma Specialist in improving FPGA Verification Process.■ Research and Feature Development of the FPGA Verification Environment for multiple Digital Datapath FPGA Designs (Interfacing Multiple IO Protocols to the Ethernet Backbone), using SystemVerilog (OVM).■ Research and Feature Development of the FPGA Verification Environment for multiple Digital Controller FPGA Designs (Including 1GE, 10GE, PCI-X, PCIe, JESD, SPI, I2C, and UART Interfaces), using Mixed-Language VHDL/SystemVerilog (UVM/UVMF) Testbenches■ Engineering Test Support at 100K Clean-Room Surface Acoustic Wave Module Fab. and Microwave Lab. ■ Bugs and Regression Failures Resolution and QoR Improvement in FPGA Verification Process.

Arlington, Va, Us

■ Member of the Embedded Processors & FPGA Verification Section in the Power and Electronic Systems Department of the Electrical Design Directorate at Raytheon IDS Headquarter.■ Raytheon Six Sigma Specialist in improving FPGA Verification Process.■ Research and Feature Development of the FPGA Verification Environment for multiple Digital IO2E FPGA Designs (Interfacing Multiple IO Protocols to the Ethernet Backbone), using SystemVerilog and OVM.■ Engineering Test Support at 100K Clean-Room Surface Acoustic Wave Module Lab. and Microwave Fab. ■ Bugs and Regression Failures Resolution and QoR Improvement in FPGA Verification Process.

■ Member of the Technology Team.■ Research and Feature Development of the Carbon Model Studio’s (Cycle-Accurate Emulator) Interfacing and Accessing APIs, using C++.■ Research and Feature Development of the internal Test-Driver Code Generator for Verilog and VHDL RTL Designs used for regression test process in both C++ (for Carbon Compiler) and Verilog/VHDL (for comparison), using C++.■ Research and Feature Development of the XML Code Generator of the Design Hierarchy for Verilog and VHDL RTL Designs, using C++, used by Carbon Model Studio’s GUI Team. ■ Bugs and Regression Failures Resolution and QoR Improvement in Carbon Compiler and Model.

Us

■ Member of the Xilinx Mapper Team.■ Research and Feature Development of the Synplify-Pro/-Premier’s Xilinx Mapper for Spartan-II, Spartan-III, Virtex-4, and Virtex-5 FPGA Families, including but not limited to Logic and Sequential Optimization and Block RAM Interfacing and Mapping, using C.■ Collaborated closely with Timing Team on Synplify-Pro/-Premier’s Xilinx Mapper Timing Correlation, Forward Annotation, and Constraint Application, using C.■ Research and Feature Development of the Synplify-Pro ValuePack’s Xilinx Mapper.■ Research and Feature Development of the UCF2SDC and EDIF2SRS File Format Converters for Synplify-Pro/-Premier’s Xilinx Mapper, using C.■ Creating Specification Documents for Synplify-Pro/-Premier’s Xilinx Mapper Developing Features.■ Bugs and Regression Failures Resolution and QoR Improvement in Synplify-Pro/-Premier’s Xilinx Mapper.

Cambridge, Ma, Us

■ Summer Internship.■ Design, Implementation, and Test of the Transducers’ Driver and Microphones’ Preamplifiers PCBs, Sampling and Triggering Software Codes for an Ultrasonic Motion Capture Environment using National Instruments LabVIEW, Altium Designer (Protel), PentaLogix ViewMate, National Instruments’ and Data Translations’ Data Acquisition Boards, Logic Analyzer, Signal Generator and High-Speed Oscilloscope.■ Creating Design and Verification Datasheet and Specification.

■ Summer Internship in the Research and Development Department.■ Design, Modeling, Implementation, and Functional Verification of an MII Interface for MAC Layer of HomePLUG IC project in Verilog using MentorGraphics ModelSim and Exemplar-Leonardo, Xilinx Foundation Series.■ Design and Modeling of an RC4 Encryption Module for MAC Layer of HomePLUG IC project in VHDL using MentorGraphics ModelSim.■ Creating Design and Verification Datasheet and Specification.

■ Design, Develop, and Maintenance of an Internet Service Provider (ISP) for the Cooperating Companies and Branches.

■ Member of the Research and Development Department.■ Design, Modeling, Implementation, and Functional Verification of a Pipelined Datapath for UTS-DSP joint-project, a CISC DSP Processor Based on TI DSP TMS320C54x Architecture in VHDL using MentorGraphics ModelSim, Exemplar-Leonardo Spectrum Synthesis Tool, L-Edit Layout Tool on FPGA Flex10K250.■ Functional Verification of UTS-DSP joint-project in VHDL using MentorGraphics ModelSim.■ Creating UTS-DSP Design and Verification Datasheet and Specification.

Phd, Electrical And Computer Eng.

M.Sc., Computer Engineering (Computer Architecture)

B.Sc., Computer Engineering (Software)

Diploma, Mathematics And Physics