Pedram A. Riahi Email and Phone Number
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US Citizen, Ph.D. candidate in Electrical and Computer Engineering, Electronic Design Automation Software Engineer, with 15 years Industrial Work Experience in Raytheon IDS, a startup System Validation Software Solution Company and in a Leading Supplier of FPGA Synthesis Software Company, 5 years Academic Experience in Digital Fault Tolerance and Testability, using Cutting Edge Technologies, with 16 Published Papers in Prominent Conferences, and Skilled Digital Hardware Design and Verification Engineer with total of 20 years Work Experience in Digital FPGA and ASIC Design, Development, Simulation, Synthesis, Emulation, Verification and Test, using Current Tools and Technologies.Specialties: ■ Behavioral/RTL Modeling, Design, Implementation, Verification, Synthesis, Simulation, and Test of Digital Systems.■ HD(V)Ls such as Verilog, SystemVerilog, VHDL, and their PLIs such as VPI and VHPI, and also familiar with SystemC.■ Verification Libraries and Methodologies such as QVL, OVL, and OVM/UVM/UVMF.■ C/C++, MS-VC++, Java, VB, Perl, Matlab, HTML, and Assembly Language.
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Raytheon TechnologiesBurlington, Ma, Us
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Senior Principal Electrical EngineerRaytheon Technologies Apr 2020 - PresentArlington, Va, Us -
Senior Principal Electrical EngineerRaytheon Aug 2019 - Apr 2020Arlington, Va, Us -
Principal Electrical EngineerRaytheon Feb 2017 - Aug 2019Arlington, Va, Us■ Member of the FPGA Verification and Embedded Processing Section in the Radar Controls and Electronics Department of the Electrical Design Directorate at Raytheon IDS Headquarter.■ Raytheon Six Sigma Specialist in improving FPGA Verification Process.■ Research and Feature Development of the FPGA Verification Environment for multiple Digital Datapath FPGA Designs (Interfacing Multiple IO Protocols to the Ethernet Backbone), using SystemVerilog (OVM).■ Research and Feature Development of the FPGA Verification Environment for multiple Digital Controller FPGA Designs (Including 1GE, 10GE, PCI-X, PCIe, JESD, SPI, I2C, and UART Interfaces), using Mixed-Language VHDL/SystemVerilog (UVM/UVMF) Testbenches■ Engineering Test Support at 100K Clean-Room Surface Acoustic Wave Module Fab. and Microwave Lab. ■ Bugs and Regression Failures Resolution and QoR Improvement in FPGA Verification Process.
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Sr. Electrical Engineer IiRaytheon May 2009 - Feb 2017Arlington, Va, Us■ Member of the Embedded Processors & FPGA Verification Section in the Power and Electronic Systems Department of the Electrical Design Directorate at Raytheon IDS Headquarter.■ Raytheon Six Sigma Specialist in improving FPGA Verification Process.■ Research and Feature Development of the FPGA Verification Environment for multiple Digital IO2E FPGA Designs (Interfacing Multiple IO Protocols to the Ethernet Backbone), using SystemVerilog and OVM.■ Engineering Test Support at 100K Clean-Room Surface Acoustic Wave Module Lab. and Microwave Fab. ■ Bugs and Regression Failures Resolution and QoR Improvement in FPGA Verification Process.
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Software EngineerCarbon Design Systems Dec 2007 - Jun 2008■ Member of the Technology Team.■ Research and Feature Development of the Carbon Model Studio’s (Cycle-Accurate Emulator) Interfacing and Accessing APIs, using C++.■ Research and Feature Development of the internal Test-Driver Code Generator for Verilog and VHDL RTL Designs used for regression test process in both C++ (for Carbon Compiler) and Verilog/VHDL (for comparison), using C++.■ Research and Feature Development of the XML Code Generator of the Design Hierarchy for Verilog and VHDL RTL Designs, using C++, used by Carbon Model Studio’s GUI Team. ■ Bugs and Regression Failures Resolution and QoR Improvement in Carbon Compiler and Model.
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Synthesis DeveloperSynplicity, Inc. Oct 2005 - Nov 2007Us■ Member of the Xilinx Mapper Team.■ Research and Feature Development of the Synplify-Pro/-Premier’s Xilinx Mapper for Spartan-II, Spartan-III, Virtex-4, and Virtex-5 FPGA Families, including but not limited to Logic and Sequential Optimization and Block RAM Interfacing and Mapping, using C.■ Collaborated closely with Timing Team on Synplify-Pro/-Premier’s Xilinx Mapper Timing Correlation, Forward Annotation, and Constraint Application, using C.■ Research and Feature Development of the Synplify-Pro ValuePack’s Xilinx Mapper.■ Research and Feature Development of the UCF2SDC and EDIF2SRS File Format Converters for Synplify-Pro/-Premier’s Xilinx Mapper, using C.■ Creating Specification Documents for Synplify-Pro/-Premier’s Xilinx Mapper Developing Features.■ Bugs and Regression Failures Resolution and QoR Improvement in Synplify-Pro/-Premier’s Xilinx Mapper. -
Design EngineerMitsubishi Electric Research Labs (Merl) Jun 2005 - Sep 2005Cambridge, Ma, Us■ Summer Internship.■ Design, Implementation, and Test of the Transducers’ Driver and Microphones’ Preamplifiers PCBs, Sampling and Triggering Software Codes for an Ultrasonic Motion Capture Environment using National Instruments LabVIEW, Altium Designer (Protel), PentaLogix ViewMate, National Instruments’ and Data Translations’ Data Acquisition Boards, Logic Analyzer, Signal Generator and High-Speed Oscilloscope.■ Creating Design and Verification Datasheet and Specification. -
TaNortheastern University 2000 - 2005
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Design EngineerValence Semiconductor Jul 2001 - Aug 2001■ Summer Internship in the Research and Development Department.■ Design, Modeling, Implementation, and Functional Verification of an MII Interface for MAC Layer of HomePLUG IC project in Verilog using MentorGraphics ModelSim and Exemplar-Leonardo, Xilinx Foundation Series.■ Design and Modeling of an RC4 Encryption Module for MAC Layer of HomePLUG IC project in VHDL using MentorGraphics ModelSim.■ Creating Design and Verification Datasheet and Specification.
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Network AdministratorSunfire Co. Apr 2000 - Aug 2000■ Design, Develop, and Maintenance of an Internet Service Provider (ISP) for the Cooperating Companies and Branches.
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Design EngineerElectro-Techniques Inst., Vlsi Circuits And Systems Lab. Sep 1997 - Aug 2000■ Member of the Research and Development Department.■ Design, Modeling, Implementation, and Functional Verification of a Pipelined Datapath for UTS-DSP joint-project, a CISC DSP Processor Based on TI DSP TMS320C54x Architecture in VHDL using MentorGraphics ModelSim, Exemplar-Leonardo Spectrum Synthesis Tool, L-Edit Layout Tool on FPGA Flex10K250.■ Functional Verification of UTS-DSP joint-project in VHDL using MentorGraphics ModelSim.■ Creating UTS-DSP Design and Verification Datasheet and Specification.
Pedram A. Riahi Skills
Pedram A. Riahi Education Details
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Northeastern UniversityElectrical And Computer Eng. -
University Of TehranComputer Engineering (Computer Architecture)
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Isfahan UniversityComputer Engineering (Software)
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Kharazmi (Mofateh) HighschoolMathematics And Physics
Frequently Asked Questions about Pedram A. Riahi
What company does Pedram A. Riahi work for?
Pedram A. Riahi works for Raytheon Technologies
What is Pedram A. Riahi's role at the current company?
Pedram A. Riahi's current role is Sr. Pr. Electrical Eng. at Raytheon.
What is Pedram A. Riahi's email address?
Pedram A. Riahi's email address is pe****@****eon.com
What is Pedram A. Riahi's direct phone number?
Pedram A. Riahi's direct phone number is (781) 522*****
What schools did Pedram A. Riahi attend?
Pedram A. Riahi attended Northeastern University, University Of Tehran, Isfahan University, Kharazmi (Mofateh) Highschool.
What are some of Pedram A. Riahi's interests?
Pedram A. Riahi has interest in Activehdl, Fortran, C/mpi, L Edit, Ms Visual Studio, Regular Expressions, Hyperlynx, Hspice, Certe, Exemplar Leonardo.
What skills is Pedram A. Riahi known for?
Pedram A. Riahi has skills like Fpga, Verilog, Vhdl, Simulations, C++, Modelsim, Computer Architecture, Asic, C, Xilinx, Matlab, Programming.
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