Peer M. Email and Phone Number

Description:Involved in subsystem front end verification of NAND Flash controllers.Role:Guide and set the direction for the verification effort within NAND Flash Controller verification projects that the team undertakes.Provide verification support to design projects by simulating, analyzing, and debugging pre-silicon full chip designs.Develop Test cases/Stimulus to increase the functional coverage for all NAND Controllers and emerging memory architectures and features.Participate in developing verification methodology and verification environments for sophisticated products.Develop and maintain test benches and test vectors using simulation tools and run regressions for coverage analysis and improvements.Manage a highly-skilled, NAND verification team.Involved in detailed design discussions and decisions and confirm design compliance to Micron’s quality standards.Supervise progress and report metrics to project and executive management.Resource and roadmap planning.Mentor and supervise the team.Collaborate with cross-functional leaders across the country to drive optimized features, performance, cost, and time-to-market.Build and grow a high-impact team of elite talents, encouraging an environment of excellence, innovation, and collaboration.

Description:Involved in verifying the calibration algorithms of DDR4 and LPDDR4 by modelling delays in between the controller and DDR model path.Role:Responsible for providing support to team members to make them progress in their work.Responsible for providing weekly status and ETAs for ongoing tasks to management.Responsible for creating the test plan, coding test bench & test cases, writing coverage, creating scoreboard flows.Responsible for completely verifying the planned features with 100% code and functional coverage.Responsible for writing directed tests/sequences for some corner cases, identified by the designers after reviewing code coverage.Responsible for reviewing the test plan and scoreboard code for other features assigned to other team members.Responsible to cross check all release tasks done against release checklist.

Description:Involved in IOSF2AXI bridge IP verification. IOSF (Intel On-chip System Fabric)cis Intel’s internal protocol. This IP makes IOSF compliant components to communicate to AXI compliant components.Role:Responsible for developing test bench from scratch and integrating BFMs.Responsible for creation of test plan, writing test case, writing coverage, creating scoreboard flows.Responsible for completely verifying the assigned features with 100% functional coverage.Responsible for writing directed tests/sequences for some corner cases, identified by the designers after reviewing code coverage.Responsible for reviewing the test plan and scoreboard code for other features assigned to other team members.Helping managers in monitoring the verification progress weekly basis. (Progress graphs are automatically generated by perl script and sent via mail)

#1 Description:Involved in verification of wireless SOC with primary activities including Chip Rate Processor block verification.Role:Responsible for the verification of Chip Rate Processor (CRP) module in a wireless SOC.Completed cluster level verification of CRP Bridge, which routes traffic to one of the internal CRP blocks.Involved in writing verification plan, creating test cases and verifying DMA.#2 Description:Involved in verification of UVM based CPRI VIP development.The Common Public Radio Interface (CPRI) is an industry cooperation aimed at defining a publicly available specification for the key internal interface of radio base stations between the Radio equipment Control (REC) and the Radio Equipment (RE).Role:Run existing test casesDebug the failures (if any) and report to designers.

# Involved in multiple activities with help from senior team members.Wrote C based tests for SoC verification. Learnt AMBA AHB and AXI protocols while debugging the issues.Wrote System Verilog assertions for some of the small modules in design.Wrote SV test cases for sub system verification.Optimized test cases to maximize success of manual test cases.Conducted regression testing and submitted observations to design team.RTL integration and unit level verification.Ran Zero delay and Timing simulations of Design using net lists (GLS).Root cause analysis of test failures and debug.Debugged issues in Gate Level Simulations