Ardavan Pedram Email & Phone Number

Santa Clara, CA, US

Stanford, CA, US

Director of Prism Projecthttps://web.stanford.edu/~perdavan/PRISM/

Stanford, CA, US

https://cs217.stanford.edu/

Stanford, CA, US

Hardware Accelerators for Machine Learning (CS 217)https://cs217.stanford.edu/

Stanford, CA, US

Hardware Accelerators for Machine Learning (CS 217)https://cs217.stanford.edu/

Ridgefield Park, NJ, US

1- Spearheaded the definition, technical management, roadmap development, and team alignment for the next-generation algorithm/architecture codesign of the AI/HPC data center accelerator.2-Led the codesign effort for hybrid (structural) sparse accelerator core architecture for CNNs and LLMs3-Conducted comprehensive workload analysis on HPCG/Stream/FFT and.

Sunnyvale, California, US

1-Led technical management, orchestrated roadmap development, and fostered team alignment for the co-design of next-generation algorithm and architecture, encompassing computer core, memory hierarchy, and interconnect components.2-Architected the memory hierarchy of processor core optimized for mapping of DNN kernels.3-Designed the compute datapath of the.

Sunnyvale, California, US

1-Implemented, and tested all of the special math functions for the internal low-level C++ language usingpiecewise-polynomial approximation and Newton-Raphson methods2-Developed a generalized Python test framework for multi-input multi-precision evaluation of floating-point arithmetic implementation of special functions and their relative error.3-Performed.

Santa Clara, California, US

1-Led the Implementation of various flavors of the fast Winograd convolution methods with their tradeoffs to improve inference performance by 3X.2-Successfully demoed Winograd convolution optimization on the Movidius architecture.3-Analyzed and optimized linear algebra and CNN library implementations for custom processors.

Austin, TX, US

Lead several projects involved with graduate students1-Static task scheduling of Linear Algebra kernels on heterogeneous systems2-Algorithm/Architecture codesign of a Multi-core Matrix Factorization Accelerator from floating-point unit design for special functions up3- Convolutional Neural Network Accelerator Design4-Integration of the Linear Algebra.

Austin, Texas, US

Designed the architecture of a multicore hybrid Linear Algebra / FFT accelerator from the ALU up to the on-chip network with a 10X better power/performance profile compared to state-of-the-art off the shelf solutions.

Burlington, Massachusetts, US

Research on the power, performance, and area trade-offs of various Xilinx FFT and FIR IP cores for Matched Filter DSP block. Implementation and verification of Matched Filter and Parabolic Peak detector blocks with dynamic window size power estimation design using Xilinx ISE on ML-605 evaluation board with Virtex-VI FPGA.Researched and studied the.

Doctor Of Philosophy (Phd), Computer Engineering

Msc, Computer Engineering