Perry Lea Email & Phone Number

Palo Alto, Ca, Us

HP Advanced Computing Solutions Chief ArchitectMy play space includes: pathfinding leading technologies, machine learning systems, high performance computing, scientific computing, medical imaging, and Hollywood studio creation machines.

Boise, Idaho, Us

Non-profit BoD work promoting and supporting women in STEM.

Eagle, Idaho, Us

Founder and CEO providing private consulting and peer review services for investment groups, technology purveyors, and government leaders.• Specializing in the analysis of: silicon process trends, memory systems trends, CPU technology and markets, emerging computer architectures, edge computing and IOT, communication technologies (5G, cellular, Bluetooth, Zigbee, mesh, LoRaWAN, Sigfox), machine learning applications and expectations, 2D and 3D Imaging and vision technologies,software economies, micro and macroeconomic trends and obstacles for technology adoption, andemerging technical review.• Providing consulting and contractual services for business development in areas of Internet ofThings, sensor systems, and computer architecture.• Providing engineering design reviews in IoT, communication systems, computer architecture, and imaging systems, and digital security.• Expert witness in areas of semiconductor design, CPU architectures, memory systems, and IoT.• Providing novel solutions in the area of cost, power, and performance for edge-based intelligencesystems.

Redmond, Washington, Us

Architecture leader for next generation Xbox consoles, accessories, and hyperscale architectures (Azure Cloud). Technology leader overseeing next generation Xbox architecture.Created and formed the architecture leadership team of Xbox business unit. Ownership of silicon design, advanced ML, communications systems, embedded systems, audio and video systems, advanced rendering, hyperscaler CDN systems, novel storage architectures, and a myriad of bleeding edge technologies.Cross organizational work throughout Microsoft business units. Specific charter on silicon reuse, IP reuse, and advanced packaging/multi-die architectures. Representative to Microsoft Technology Development Council support Azure, ML, client, and hyperscaler futures. Technical counsel for Xbox senior leadership team (CVP level).Collaboration with Microsoft Research in technology incubation and technology transfer.Managed partnerships with all major processor, storage, networking, GPU, and NPU vendors.Xbox patent review board for IP filing, licensing, and review.

Redmond, Washington, Us

Principal Technologist and Systems Architect for Microsoft Xbox, Endpoints, and Devices. Directed and led teams in Xbox silicon, firmware, communication systems, immersion cooling, and hardware design.Liaison and technology transfer governance from Microsoft Research to productization.Emerging technology catalyst and architect responsible for driving new technologies to productization. Partner with ARM, AMD, Micron, Samsung, Hynix, Realtek, Broadcom, Mellanox, and ZT Systems.Design of xCloud hyperscale systems and datacenter architecture: hardware, communication systems, storage systems.

San Jose, California, Us

ConvIOT delivers data enabled performance improvement by leveraging the Internet of Things (IoT), situational awareness software, M2M, Robotics, and other applicable technologies. I founded ConvIOT with Terri Foudray in 2018. My vision for ConvIOT is to directly address the issues confounding the industry in enabling connected machinery. There is certainly hype and a profound amount of marketing around IoT, Edge Computing, and AI. As a practitioner of engineering at hyper-scale capacity, I advocate the separation of hype from reality. ConvIOT removes the complexity of connecting and enabling devices at the edge. Building mass scale IoT and edge intelligence requires cross-disciplinary skills in embedded systems, sensors, cloud and fog dynamics, situational awareness, power, security, and communication theory. It is my vision to build a company that will enable enterprises to connect and extract value from the edge.

Boise, Idaho, Us

C-Level Accountability• Technical council to C-Level staff. Reporting to CTO.• Defined and developed the business case and technology for an IoT solution with growth plans of30% YoY.• Led all customer interactions and relations to help solve large scale commercial and industrial IoT/ fog compute challenges: industrial, smart city lighting, agriculture, healthcare, defense, and retail.• Developed industry relationship: ATT and Verizon (5G LTE), Amazon, Microsoft, IBM, andThingworx, Ericsson, ARM, and HPE.• Lead the development of near range communications, AWS SaaS based IoT management plane,and software defined micro-segmentation of IoT devices in mass deployments with minimalsupervision.• Advisor for emerging technology as well as potential mergers and acquisitions.Technical Management• Managed direct team of engineers is SaaS front end and hardware edge development. ManagedSOW and budget for contractual engineering services.• Successfully built a business model for positive ROI and reduced OPEX with IoT edge computing.• Researched and developed industry leadership in Bluetooth 5 with early pilot technology.• Senior technical staff to a multi-regional team of 160 engineers. Accountable for strategicdevelopment, path-finding, sensor to cloud partnerships, and research in advances for IoT & edgecompute systems.Thought Leadership and Evangelism• Fortune 50 customer facing technologist. Liaison to DoD, NSF and DARPA. Ownership ofacademic and university relationships in areas of adaptive network security and fog compute.Invited conference speaker and panelist. Provide thought leadership in whitepapers, books, CIOMagazine, and press interviews.• Director of intellectual property process, council, and protect growth for IPO candidacy.

Boise, Idaho, Us

Accountability• Delivery, architecture, and business case models of PIM technology.• Provided expert guidance on real-world application of machine learning, inference engines,computer vision, imaging, and security (bloom filters and SHA) to novel PIM architecture.• Senior technical council for Micron executive staff and technical lead for staff of 40 (DRAMdesigners, computer architects, computational mathematicians, logic designers, system architects,and software engineers).• Responsible for pathfinding, roadmaps, architectural definition, business development, design, anddelivery of a game changing computing systems directly attacking Moore’s Law and DennardScaling through processing in memory (PIM) technology within a DRAM process.Technical Management• Managed direct staff of research engineers, computational scientists, and university interns.Managed budget of $500,000 for contractual engineering services and academic research.• Chartered with team construction and composition. Participated in the merger-acquisition-integrationof Convey Computers into group.Business Development• Development of new technologies, intellectual property, defensive publications, and creation ofnew markets for emerging computational memory.• Managed broad and complex technical partnerships across academia, software providers, siliconpartners, and government agencies.Thought Leadership• Principle investigator for National Geospatial Intelligence Agency, Microsoft Research, AllenInstitute, etc.• Worldwide technical evangelist, business developer and strategist for processing in memorysolutions.• WW Publication of PIM technology within IEEE Micro.

Palo Alto, Ca, Us

Chief Architect of Embedded Systems – Imaging and Printing GroupAccountability• Technical council for executive staff and division vice president/general manager.• Accountable for over 40 cradle-to-grave product launches with over 30 million products shipped.• Responsible for ASIC, board level componentry, low level firmware and top of stack firmwarewith 22 development projects in flight.• Delivery of $130M in cost savings via ASIC super-integration and novel co-simulation tactics.• Responsible for new venture investigations into A3 partnerships with Sharp, Canon, etc.Technical Management and Leadership• Strategist and lead for multi-discipline R&D lab comprising 500+ engineers and scientists for HPbrand. Managed the Firmware Architecture Forum and Hardware Architecture Forum.• Direct manager of a senior team of 10 master architects involved in hardware and firmware design.Thought Leadership• Advanced HP’s strategic interests through architecting memory technologies, SOC architecture,HP TechCon, advancing HP Labs memristor storage applications and IP development.• Drove patentable innovation from research phase to products in ASICs, imaging, security, andpower with Purdue, Rochester Institute of Technology, BSU, and Columbia University.• Research, design, prototyping, and evangelizing novel imaging, security, multi-touch and displaytechnologies, and embedded technologies pervasive to HP.• Developed and architected HP’s novel Symbiote security platform.Corporate Partnerships• Developed strategic partnerships: ARM, Vivante, Microsoft, Intel, Marvell, & PMC-Sierra.

Palo Alto, Ca, Us

Principal hardware/firmware architect for Embedded Systems Lab.Accountability• Responsible for all future digital imaging architectures including parallel ink arrays, dry electrophotographicdevices, and capture systems. Responsible for 2.5M LOC and 25M gate SOCs.• Successfully deployed 37 independent product lines within a 6-year period ranging from smallbusiness imaging systems to enterprise/industrial copiers, printers, and network scanning.• Supervised architectural direction over imaging subsystems with a staff of 36 engineers.• Developed architecture to meet requirements, participated in development of firmware, androutinely debugged the most complex hardware-firmware problems.Technical Leadership• Institutionalized lab wide agile development methodologies and service orientated architectureprinciples. This effort resulted in a 2X reduction in defects and improved time to market by 50%.• Developed system wide process and schedules for new product turn-on from ASIC architectureand co-development through product launch which compressed ASIC turnon schedules by 75%with zero spins.• Researched and developed: CODEC acceleration through SIMD reinforcement, compileroptimization technology, voltage and frequency shifting code for efficient power usage for EnergyStar certification, hardware acceleration for rendering, and inter-processor communication.

Palo Alto, Ca, Us

Team Lead and Architect for Core Technology LaboratoriesAccountability• Development and turnon of HP’s first parallel inline laser system. Lead the design of: four planeparallel printing, high performance rendering, memory layout structures, and low-level code.• Led a team of six engineers in the delivery of initial board turn-on, new ASIC verification,schedules, requirements, and processor turn-on.• Responsible for LaserJet 4600, 5500, and 9500 product delivery.

Palo Alto, Ca, Us

Accountability• Designed a state of the art system to train and teach en embedded rendering system how to race a laser beam in real-time through early ML and inference.• Designed a system-wide discrete event simulator to explore new architectural concepts.• Directly responsible for the development of: novel image compression technologies, parallelalgorithms, memory throughput enhancement (MEt), processor analysis, and compiler efficiencies.• Technical lead for the EPFL university research program for 3 successful projects: DSP/MMXincorporation into the HP graphics engine layer, compiler improvements outside of assembly forMIPS processors, and display list optimizations.• Coordinated research work with HP Labs team in Palo Alto and Bristol.

Palo Alto, Ca, Us

Accountability• Responsible for the delivery of the LaserJet 4j drivers. Software design and debug.• Developed a test strategy and test bed for confidence testing of the Windows drivers.• Worked with and mentored Chinese Academy of Science for contractual support of HP drivers.

Milwaukee, Wi, Us

Verona, Veneto, It

Eng D, Electrical Engineering

Certificate Program - Currently Enrolled, Machine Learning And Data Science

Ms, Computer Engineering

Bs, Computer Science

Building Innovative Leaders Program, Mba