Pete Dice Email & Phone Number

El Dorado Hills, California, Us

Managing an experienced team of engineers engaging new customers and partners to onboard them on Balize’s Hardware and Software offerings. Collaborating with existing customers to ramp and win in their respective market segments

Serving as lead Technology Consultant for startups and their customer base. Providing system-level decision making and guidance to small companies to bring their best solutions to market. Providing experienced insights for Roadmaps , customer journeys, architecture, and engineering problems and opportunities to build, grow to the next level, reduce cost and increase operational efficiencies and profit margins.

Santa Clara, Ca, Us

Helping Ampere grow from startup to mature partner and vendor to the data center and server compute ecosystem. Lead SW planning for next-generation ARM-based SoC FW & SW stacks. Bridging between the product, architecture and engineering execution teams to ensure that cloud-native computing solutions are best in the datacenter. Created and owned development tools roadmap and drove engineering execution for Ampere Computing, allowing for enabling & debugging of motherboard subsystems such as DDR and PCIe Margining, as well as streamlining AVL testing with global execution teams. Working with customers to deliver product training, drive proof of concepts through to production. Creating material for customers to avoid common pitfalls of older/obsolete Operating systems and compilers. Providing silicon roadmap input to management to prioritize feature scalability into datacenter and IOT edge spaces for high end solutions.Working with industry luminaries and customers, created a scalable open source LinuxBoot solution for Ampere Altra platform which is 90% reusable across next generation SoCs. This lowers adoption costs and speeds time to market for new customers in both the IOT space and the Datacenters, while provide transparency into lower level firmware.

Cork, County Cork, Ie

Engaging with the US top retail customers to bring new visual AI & Machine Learning solutions to retails stores, their supply chain, and embedded solutions.. Lead Teams to deliver AI/ML algorithms based on Nvidia GPU stacks. Created product roadmap for cloud-based application to establish regular release cadence which enabled customers to plan on integration/delivery proactively. Collaborated with sales and customer success teams to establish quarterly releases of a stable software image for older generation models, allowing for long life while simultaneously develop and deliver ML models for new generation solutions. Revitalized on-premise hardware recommendations with partners (Dell, Lenovo, Supermicro, HPe) for system integration with customer IT teams providing reduced Total Cost of Ownership (TCO) and faster time to market for everseen. Lead a diverse set of engineering teams in Romania, investing heavily in process improvements up bring this high-potential startup toward a full software factory with CI/CT/CD agile methodology.

Boise, Idaho, Us

Leading cross geo teams of engineers to create tools and drivers for Micron SSDs' manufacturing, validation, and production environments. Working closely with management, cross functional teams, to provide OEMs' with integration, debug, and maintenance and quality solutions. Defining the roadmap for software for client, consumer, embedded and enterprise SSDs.

Dublin 11, Ie

Hosting and leading numerous Hackathons across Dublin and London for smart cities, smart Agriculture. Guiding groups of 150+ local makers and professionals to solve BIG problems for multinationals and cities through innovation, user-centered design and cheap/available IOT technology. Worked with companies such as PCH and other investors to champion and award innovation helping foster growing startups in an accelerator network to scale and ramp innovative new products. Advised startups on go-to-market strategies and used professional network to ‘match-make’ startups to ecosystem partners.

New York, Ny, Us

As Ireland country managing director of a $400m company, and leading teams of 150+ software engineers across Europe and the US, we built new advance Agile methodologies across all engineering teams to drive up Quality and on-time delivery through a CI/CT/CD pipeline. We stabilized and optimized a $20M Software development life cycle capacity plan for architecture, design, development, test, deployment, and support for VeriFone Payment terminals. This generated $1.2B in revenue yearly. Collectively, the team launched a record number of payment terminals per year (more than 10 time more models than previous years), saving the company millions. Using real-time tools we provided upper level management with transparency of our pipline. We lowered local Ireland-based headcount cost by a third by leveraging Irish grants. We reduced hardware factory throughput times by 50% by applying lean methodology to the software execution requirements. Reduced boot times by 50% and increased battery life by 3x saving per unit manufacturing cost.

San Jose, California, Us

Managed the Enterprise Licensing Technology team, a small dedicated team of 10 senior engineers and architects. Integrated new subscription-savvy licensing and telemetry mechanisms for the tracking and tracing of Symantec product deployments and usage, both in the field, and the cloud; providing the capability to turn products off/on, on-demand, anywhere. Architected the Next Generation licensing technology for subscription services and legacy on premise installation of existing mainstream cybersecurity software. Added usage telemetry and enforcement across the Symantec enterprise portfolio for tighter licensing and sales tracking. Drove a technology conversion and change management program with Sales, Renewals, Customer Care and Technical Support.Represented Symantec as treasurer of TagVault, leading technological advancement in software ID tags/tools as a global cybersecurity leader. Oversaw finances, approved organizational direction, provided technical input to new specifications and working groups at TagVault.org, primarily focused on software identification tags (as specified by ISO/IEC 19770-2) and software entitlement tags (as specified by ISO/IEC 19770-3).

Santa Clara, California, Us

Demonstrated ability in integration and global deployment at a large scale, across a complex ecosystem --from product vision/ strategy to developing software for emerging technologies such as Intel IoT gateways, sensor networks and wearable devices. Accelerated design and deployment of IoT and Wearables across vertical markets (Medical, Retail, and Manufacturing) providing embedded expertise, development and platforms that deliver connected, secure and remotely managed IoT devices--vastly reducing time to market. Drove Intel’s education initiatives to improve user experience in Galileo, Edison and IoT gateway solutions--and make Intel architecture the platform of choice for makers and developers.• Launched Intel® Quark™ Intel’s first generation SoC and newest family of microprocessors• Invented the Intel® Galileo™ development board and drove product portfolio market adoption through leading customer workshops• Drove IoT business solutions through designs across industrial applications • Led market analysis and technical feature identification for a new embedded product portfolio • Developed a freemium SW strategy that easily scales Intel IoT gateway features across product lines into Quark, Atom, and Core based platforms• Architected “Moon Island” software stack and business model for connected, managed, secure and intelligent platforms collaborating with Linux Kernel maintainers, Wind River and McAfee which is now the cornerstone of Intel’s IoT Gateway solutions• IAA (Intel Achievement Award) recipient May 2014 for Galileo innovation

Santa Clara, California, Us

Responsible for UEFI and OS architecture of all IO controllers, manageability engine and firmrware interfaces on the intel south-bridge components of Ultrabooks, all-in-ones, desktops, laptops, and servers. Lead technical team in to streamline mainstream BIOS to sub-second boots and 100mS resume speeds. Drove strategic pull in and refining of intel responsiveness targets and key features for 2011 through 2015 platforms to enable new user experiences in computing.• IAA (Intel Achievement Award) recipient May 2013 for developing Intel Fast Boot technology -- working with intel and Microsoft teams to get Windows 8 to boot 3x faster than Windows 7 • Authored “Quick Boot: A Guide for Embedded Firmware Developers.” http://www.amazon.com/Quick-Boot-Embedded-Firmware-Developers/dp/1934053406• Maintained Long term roadmap alignment with key customers like Apple, Google, Microsoft, Asus, Dell, HP, IBM, Lenovo, Acer, Samsung, LG, Cisco, Huawei and Toshiba

Santa Clara, California, Us

Managed an international team of software architects responsible for telecommunications silicon firmware and platform software stacks including Intel® Quick Assist technology and the carrier grade 4-in-1 architecture strategy. Architected the “Boot Loader Development Kit” and brought the product to market with BIOS vendors, OS Vendors, motherboard manufacturers.

Santa Clara, California, Us

Created Firmware and Linux SW architecture for integrated ARC based 3rd party audio engine for the Intel phone platform. Researched audio codec middleware vendor options and led technical negotiations with business development units. Led the team of senior firmware and BIOS engineers through architecture, design, validation and launch of new firmware for a heterogeneous multi-processing system.

Santa Clara, California, Us

Senior account manager and firmware technologist for: Intel Xeon's inter-processor communications protocol (QPI) and UEFI reference code. Responsible for resolving unique high volume Server OEMs customer platform design issues to enable them to get to market with world-record setting performance. Participating in industry technical forums to provide direction and influence management executives to produce a cohesive strategies cross segment and cross industry.

Santa Clara, California, Us

Managed a world-wide organization of 12+ principal engineers and senior Architects design SW for ARC based solution in intel chipsets for Telco customers like Cisco, Huawei, Juniper Networks, etc. Created Data plane development kit (DPDK) to handle bare-metal applications with low latency and fast access to on-load and offload engines. Created and Fostered Intel Quick Assist Technology (QAT) and User forum to support cross multiple company SDK and interfaces.

Santa Clara, California, Us

Managed a world-wide organization of 60+ engineers/managers over 9 sites and 6 countries, providing scalable support solutions for Intel and ARM-based XScale platforms to Consumer electronics set top box and digital TV customers.Manage Digital Home Software Engineering team of 25 engineers and managers in US and PRC providing scalable system software solutions for Intel and XScale platforms to Digital Home customers. Managed first level managers who are responsible for defining SW requirements, development of Linux and Windows* CE OS drivers and board support packages, providing custom embedded firmware solutions including video BIOS, and supporting OEM, BIOS, Middleware, and OS Vendors.

Santa Clara, California, Us

Managing PC Client and Server BIOS Applications Engineering team of 10 across US and Taiwan, providing timely, accurate to OEM & BIOS Vendor customer support related to BIOS/Firmware issues on Enterprise and Desktop chipsets and related initiatives. Responsible for development of Intel & Industry collateral (BIOS specifications, reference code, industry specifications). Interfacing with cross product groups, cross functional teams such as engineering, validation, product, and marketing teams.

Santa Clara, California, Us

Provided technical leadership in the customer SW development group and platform support teams on BIOS validation. Created industry leading tool “Self Test tool” to allow customers to debug their own BIOS issues. Networked with cross company engineering and validation teams in creation and support of common framework for testing of Intel products. Responsible for discovery, scope, development, validation, training, and support for BIOS Vendors and MNC’s, to provide intel Self-Test Tools. Supervised BIOS testing of Intel chipset system BIOS for BIOS Vendors.

Santa Clara, California, Us

Responsible for initial discovery, code development and validation, documentation, training, and maintenance of the intel chipset test tools. This real-mode test tool, developed in ‘C++’, was used by intel technicians in system-level BIOS testing. Led test stage operations, managing engineers, and technicians supporting customer for system test stage operations. Team provided external customer validation for intel CPU/chipset series platforms. Lead testing at numerous industry events (ACPI, AGP, USB, PCI, Wired for Management, and DMTF).

Bethesda, Md, Us

Supervised technicians testing NiH2, NiCd, and Super NiCd rechargeable batteries used on commercial and civilian telecommunication satellites. Troubleshot HW & SW failures occurring in test units and antiquated automated test systems. Disposition and authorize reworking/retesting of flight, non-flight, qualification, life-qual and R&D batteries. Certified battery and battery sub assemblies for use on commercial, government, and civilian spacecraft. Wrote and reviewed electrical and environmental test procedures for shock, vibration, and thermal vacuum. Reviewed battery designs for testability. Designed and maintained battery test facility HW and SW. Interacted with design and manufacturing engineers, production controllers, program management offices and Lockheed Martin customers on a daily basis.

Provided production support for second and third shift manufacturing of custom HF switching and DC power supplies. Represented test engineering on new product teams. Reviewed customer specifications and interfaced with design engineering in development of test specifications. Coordinated with industrial engineering and manufacturing personnel in the writing of procedures per ISO-9000. Designed, built, installed, and maintained test fixtures and facilities. Worked with quality engineering in test data analysis to reduce cycle time on high volume contracts to increase profit margins.