Peter Bayley
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Peter Bayley Email & Phone Number

Principal FPGA and DSP Engineer at Forward Edge-AI
Location: Iowa City-Cedar Rapids Area, United States 13 work roles 2 schools
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Current company
Role
Principal FPGA and DSP Engineer
Location
Iowa City-Cedar Rapids Area, United States

Who is Peter Bayley? Overview

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Peter Bayley is listed as Principal FPGA and DSP Engineer at Forward Edge-AI, based in Iowa City-Cedar Rapids Area, United States. AeroLeads shows a matched LinkedIn profile for Peter Bayley.

Peter Bayley previously worked as Principal FPGA Engineer at Technical Link @ Banc3 For The Us Space Force and Lead FPGA Engineer at Realtime Dynamics Llc. Peter Bayley holds B.S. Electrical Engineering, Hardware Engineering, Graduate from Oregon Institute Of Technology.

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Forward Edge-AI

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About Peter Bayley

I am a Senior FPGA Engineer and a mission driven individual motivated by meaningful work with a measurable impact, for which I will stop at nothing to solve even the most complex technical challenges.My areas of specialization include Data Converter Array Synchronization, Deterministic Latency datapath design, advanced clocking synchronization, and low latency & coherent parallel data path design of all types from RF to high-speed serial. I have a fanatical dedication to enhancing Deterministic Latency and Performance of Networking and datapath subsystems, alongside control systems that require advanced intercommunication to perform reliable actuation.I am skilled in Digital Signal Processing, FPGA RTL Design, AI, Low Latency and Deterministic AI, Phased Array Radars, Phased Array RF Beamforming, High Speed Multigigabit Transceiver PCB Schematic Design & Layout, Multigigabit Transceiver Physical Coding Sublayer Datapath Systems, High Speed Sensor Interfacing, and High Reliability Control System Design and Actuation.The output of my work is reflected not only in achieving the goals of projects to which I am a part of, but also by the advancements of our understanding and application of principles of engineering through my patents and publications. You can expect to witness my influence and feel the impact of my measurable outputs anywhere you find me, because my drive for advancing my art and achieving your goals to their highest degree is perpetual.

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Peter Bayley's current company

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Forward Edge-AI
Forward Edge-Ai
Principal FPGA and DSP Engineer
Cedar Rapids, IA, US
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13 roles · 18 years

Peter Bayley work experience

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Principal Fpga Engineer

Technical Link @ Banc3 For The Us Space Force

Princeton, New Jersey, United States

Working on several important projects for the US Space Force with BANC3 through Technical Link. My work involves developing, testing, and deploying advanced Cognitive Radio DSP algorithms for Demodulation, Navigation, and Recompilation.

Lead Fpga Engineer

Realtime Dynamics Llc

United States

• RTL development of a custom AI model with fixed latency for Object Tracking based on YOLOv3, ShuffleNetv2, and Dirac-DeltaNet architecture. • RTL development of a low & deterministic latency IEEE compliant 10G BASE-R/KR Ethernet IP core.• Implemented reduced latency versions of the newly released IEEE Time Sensitive Networking standards such as the IEEE 802.1 QBv Time Aware Traffic Shaper.

Jan 2020 - Sep 2024

Senior Electrical Engineer

United States

Will be using my skills as an FPGA Engineer leveraging my abilities in Analog Front End Signal Acquisition, Reliable Actuation, & Digital Signal Processing to help Raytheon Technologies succeed on a variety of their critical missions. Low Latency Artificial Intelligence and Low Latency RF Signal Chains particularly concerning the use of integrated high speed Data Converters in the RFSOC are a part of this work.

Oct 2022 - May 2024

Fpga Engineer Iii

Portland, Oregon Metropolitan Area

Lead FPGA Hardware Design Engineer for handheld Ultrasound Imaging Device. Breakthrough performance for portable Ultrasound by coupling an FPGA with a GPU for major data throughput enhancing image quality using AI algorithms in software for different beamforming and imaging settings while also improving deterministic performance, precision, and reliability by implementing timing critical functions and data conversion on an FPGA.

Apr 2021 - Mar 2023

Electrical Design Engineer

Fairport, New York, United States

Sep 2020 - Dec 2020

Electrical Engineer

United States

I debugged Multigigabit Transceiver datalinks between FPGAs across stacked PCBs and through optical assemblies necessary for the company’s space constrained Aerospace products. Used Altium Designer, Mentor Hyperlynx. Several problems in the system required that I design and build a new transceiver datalink of my own that could be controlled with advanced clocking methodology and from a low level for visibility and debugging prowess. I performed low-level RTL design of transceiver cores using enhanced implementations of standard protocols like Aurora and IEEE 802.3 QBv were implemented in the designs of large systems to address and resolve complex issues in these systems, thereby clearing margin in the critical design path. PCB review using Altium Designer.

Apr 2019 - Apr 2020

Federal Pathways Program Student

Vancouver, Wa

Key member and creator of The Jaguar Initiative. A multi stage initiative created by Bonneville Power Administration to create a Sequential Event Recorder than can accurately time stamp and store recordings of transfer-trip signals being sent to and from remote relays that are encrypted using the SEL Mirrored Bit Algorithm. The device must be able to successfully decrypt the data encoded in the Mirrored Bit Algorithm. Project Jaguar is significant because considering that the Mirrored Bit Algorithm is registered intellectual property of Schweitzer Engineering Laboratories, there are no off the shelf devices that can perform this task. A successful working prototype of the Jaguar has been created and tested, and the Jaguar is currently undergoing advanced development.

Jun 2016 - Feb 2020

Electrical Engineering Intern

Bonneville Power Administration

Project Jaguar.

2016 - Feb 2020

Hardware Engineer

Oregon Tech Formula Sae

Circuitry & Wiring MaintenancePCB DesignHardware Device PrototypingElectronic Speed Controller Upkeep

Apr 2015 - Jan 2020

Electrical Technician

Klamath Falls, Or

Dual employment with Sears Holdings & Basin's Best Appliance Repair Services.

Jul 2015 - Sep 2015

Electrical Technician, Home Services

Klamath Falls, Or

Repairing and sometimes re-engineering Refrigerators, Washing Machines, Dryers, and other house hold appliances. Quick response to house calls from customers in need of a technician.In training for HVAC Certification.

Jul 2015 - Sep 2015

Volunteer Group Manager

Nextstep Recycling

Directing the volunteers in their workFinding Work for the electronically minded volunteersAnswering questions and working alongside the volunteers

2009 - 2011 ~2 yrs
2 education records

Peter Bayley education

B.S. Electrical Engineering, Hardware Engineering, Graduate

Activities and Societies: OIT Honor's Program OIT Formula SAE Racing

Computer Hardware Engineering, Fpgas, Microcontrollers, Embedded Systems, Automotive Electrical Systems, Transistors

Activities and Societies: Oregon Tech Racing / FSAE, Robotics, Honors Program, Engineering Honors Program.

FAQ

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What company does Peter Bayley work for?

Peter Bayley works for Forward Edge-AI.

What is Peter Bayley's role at Forward Edge-AI?

Peter Bayley is listed as Principal FPGA and DSP Engineer at Forward Edge-AI.

Where is Peter Bayley based?

Peter Bayley is based in Iowa City-Cedar Rapids Area, United States while working with Forward Edge-AI.

What companies has Peter Bayley worked for?

Peter Bayley has worked for Forward Edge-Ai, Technical Link @ Banc3 For The Us Space Force, Realtime Dynamics Llc, Raytheon Technologies, and Yorultrasound.

How can I contact Peter Bayley?

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What schools did Peter Bayley attend?

Peter Bayley holds B.S. Electrical Engineering, Hardware Engineering, Graduate from Oregon Institute Of Technology.

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